Added PE layouts for derecho, removed PE layouts for cheyenne, updated testlist to move cheyenne_* tests to derecho_*, and then moved derecho_pgi to derecho_nvhpc. I also updated generate_pop_decomp.xml to include a 128 PE layout for the gx3v7 grid as well as some large PE layouts for tx0.1v3.
Testing:
I ran aux_pop and verified that all intel tests ran successfully; the gnu test built but did not run. I will investigate that later if it persists in the alpha testing for cesm2_3_alpha17 series. I also did some performance testing, and can report the following throughput in different configurations (from SMS_Ld20 and SMS_Ld20_D tests using the pop/performance_eval testmod directory)
Resolution
C compset
G compset
C1850ECO compset
G 1850ECO compset
T62_g37
256.98 SYPD
249.72 SYPD
110.17 SYPD
187.14 SYPD
T62_g17
52.60 SYPD
52.41 SYPD
26.79 SYPD
26.67 SYPD
T62_g37 (DEBUG)
35.28 SYPD
46.67 SYPD
11.16 SYPD
13.24 SYPD
T62_g17 (DEBUG)
5.53 SYPD
5.48 SYPD
2.38 SYPD
2.37 SYPD
Test status: bit-for-bit doesn't make sense in context of adding a new machine
User interface (namelist or namelist defaults) changes? None
Description of changes:
Added PE layouts for derecho, removed PE layouts for cheyenne, updated testlist to move
cheyenne_*tests toderecho_*, and then movedderecho_pgitoderecho_nvhpc. I also updatedgenerate_pop_decomp.xmlto include a 128 PE layout for thegx3v7grid as well as some large PE layouts fortx0.1v3.Testing:
I ran
aux_popand verified that allinteltests ran successfully; thegnutest built but did not run. I will investigate that later if it persists in the alpha testing forcesm2_3_alpha17series. I also did some performance testing, and can report the following throughput in different configurations (fromSMS_Ld20andSMS_Ld20_Dtests using thepop/performance_evaltestmod directory)Test status: bit-for-bit doesn't make sense in context of adding a new machine
User interface (namelist or namelist defaults) changes? None