Feature request: sample aggregation for higher sampling rates

[lsigrist]

(extracted from original request #44)

Currently, there is an argument to specify sample aggregation for rates (strictly) below 1 kHz. An option to sample at e.g. the max. frequency and aggregate the results to e.g. 100Hz would be very useful to reduce the amount of collected data without loss in accuracy.

relates to: #16 #44

[lsigrist]

@rdaforno This is a very valid question you're raising with this. The answer is far from being straight-forward.

In short: The restriction of sample aggregation to sample rates where this is strictly necessary (i.e. those below the lowest native ADC sample rate) is done on purpose. The reason is that with the currently implemented, very basic data aggregation algorithms the sample aggregation from higher sample rates is considered not advisable.

I'll try to give some insight on why this is currently considered not advisable: From a pure data processing point of view, the aggregation could be easily performed also from values sampled at higher sampling rates. However, by increasing the ADC's sample rate (compared to the minimum ADC sample rate allowing aggregation to the targeted aggregated sample rate), many other properties of the ADC change as well. In the context of sample aggregation focused at here these changes are likely do not in the interest of the user:

• An increase in the ADC's sample rate comes with an increased bandwidth of the ADC's internal filter. This results in letting pass even higher frequency signal components than the final aggregated sample rate can capture. This is problematic for the window based average down-sampling that in an increase of unwanted aliasing artifacts in the aggregated signal.
• The measurement performance for the sampled values decreases (in terms of dynamic range). This directly results in degraded performance when "aggregating" by skipping intermediate samples. Also with aggregation algorithms taking into account all values, the loss in dynamic range due to the increased ADC sample rate cannot be fully recovered computationally.

[lsigrist]

Nevertheless, I'm very curious to collect scenarios where a higher ADC sample rate (than strictly necessary for aggregating to the targeted sample rate) could be interesting, as I cannot think of one at the moment. And in particular what you presume in terms of measurement performance and usability in such situations.

With more advanced down-sampling algorithms the above listed problems can be much better controlled. Then the requested aggregation mode may represent an interesting trade-off in specific scenarios.

[rdaforno]

Thanks for the explanation.
Maybe it wasn't clear what I meant with "max. frequency". I was referring to the max. supported sampling rate of 64kHz.
The use case for sampling at 64kHz I think is clear, e.g. energy measurements for an MCU with short active periods (< 1ms).