Eawag-AppliedSystemAnalysis / Simstrat

Simstrat - 1D lake model
http://www.eawag.ch/en/department/surf/projects/simstrat/
GNU General Public License v3.0
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Output times are interfering with simulation timestep #23

Closed f-baerenbold closed 4 years ago

f-baerenbold commented 5 years ago

If a certain output time (specified in the file) is not matched by the simulation times, simstrat currently adjusts the timestep in the following way:

This is not really a neat solution for two reasons:

We should implement a timestep adjustment which does not/minimally interfere with the simulation timestep. I see 2 possibilities:

adrien-ga commented 5 years ago

Thanks for the summary, I vote for option 1 ;) - it's simpler and there's no intereference with the actually simulation

f-baerenbold commented 4 years ago

Solution 1 is now implemented on the master branch.