Formatting aligns variables across regions

[EdaphicStudio]

The following code gets reformatted unexpecedtly:

BEFORE

function testbench::new (string name, truss::interfaces_dut dut_base);
    interfaces_uart          uart_dut;
    super.new (name, dut_base);
    log_.debug ("testbench new() begin ");

    begin
        int foo = $cast (uart_dut, dut_base);
        assert (foo);
    end

    for (int i = 0; i < number_of_uarts; ++i) begin
        a_uart_group[i] = new (name, i, uart_dut.uart_interface_[i], uart_dut.uart_16550_interface_[i]);
    end

    //Now for the main chip register interface
    wishbone_driver_ = new ("WB", uart_dut.wishbone_driver_interface_1);
    begin
        wishbone_memory_bank mb = new ("main_bus", wishbone_driver_);
        teal::add_memory_bank (mb);
        teal::add_map ("main_bus", `uart_registers_first, `uart_registers_last);
    end

    top_reset_ = uart_dut.top_reset_;

    log_.debug ("testbench new() done ");
endfunction

AFTER Note that int foo is aligned with uart_dut in the outer scope

function testbench::new (string name, truss::interfaces_dut dut_base);
    interfaces_uart          uart_dut;
    super.new (name, dut_base);
    log_.debug ("testbench new() begin ");

    begin
        int                  foo = $cast (uart_dut, dut_base);
        assert (foo);
    end

    for (int i = 0; i < number_of_uarts; ++i) begin
        a_uart_group[i] = new (name, i, uart_dut.uart_interface_[i], uart_dut.uart_16550_interface_[i]);
    end

    //Now for the main chip register interface
    wishbone_driver_ = new ("WB", uart_dut.wishbone_driver_interface_1);
    begin
        wishbone_memory_bank mb = new ("main_bus", wishbone_driver_);
        teal::add_memory_bank (mb);
        teal::add_map ("main_bus", `uart_registers_first, `uart_registers_last);
    end

    top_reset_ = uart_dut.top_reset_;

    log_.debug ("testbench new() done ");
endfunction

EXPECTED: Unchanged from BEFORE

[EdaphicStudio]

Fixed in BETA10