EdaphicStudio / SystemVerilog

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`define macro parser seems broken #33

Open philipaxer opened 5 years ago

philipaxer commented 5 years ago

It seems that macros parser is not correctly implemented.

The following

`define BLA2(x,y) x [1:0]
`BLA2(logic,test) x;

evaluates to:

logic [1:0IntellijIdeaRulezzz ] x;

Additionally in the following example, BLA2 is not recognized in the third line.

`define BLA2_X(x,y) x+y:y
`define BLA2(x,y) x*y:y
logic [ `BLA2(X, Y)  ] level;