EdaphicStudio / SystemVerilog

Public issue tracker for Edaphic.Studio/SV
MIT License
0 stars 0 forks source link

Macro cannot find definition #34

Open Johnlon opened 4 years ago

Johnlon commented 4 years ago

Macro support seems realy flakey.


`define test1(expected) assign expected = 1'b1;

module testCase();

    `test1(aa, bb); // gave Unknown macro

endmodule : testCase

But if I make a random change to the name it works...


`define test1a(expected) assign expected = 1'b1;

module testCase();

    `test1a(aa, bb); // it works??

endmodule : testCase

But then make some distant unrelated change and it fails to resolve the macros again.

Seems to work one minute and not the next.

Even the files above seem to work occasionally?