Open fhuebner opened 3 years ago
same behaviour in this case:
module test;
always_comb begin
for (int i = 0; i < NUM; i++) begin end
end
endmodule : test
press enter with cursor places before the "end", result is:
module test;
always_comb begin
for (int i = 0; i < NUM; i++) begin
end // <- unexpected intention
end
endmodule : test
expected:
module test;
always_comb begin
for (int i = 0; i < NUM; i++) begin
end
end
endmodule : test
If I have these code fragment:
set the name of the task to "t", move the curser behind the semicolon and press enter, you will get this:
I would expect this (which you also get, if you select everything and then use "Reformat Code"):
Settings in intellij for the systemverilog plugin are set to:
this also happens if you try to use the block "generate endgenerate".
But it dont happen, if you write the first half like "task t();" by hand and then press enter. In this case the end will be added automatically and will be indented correctly.