EdaphicStudio / SystemVerilog

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unexpected indention after pressing enter in some autocompleted statements. #38

Open fhuebner opened 3 years ago

fhuebner commented 3 years ago

If I have these code fragment:

module test;

endmodule : test

this also happens if you try to use the block "generate endgenerate".

But it dont happen, if you write the first half like "task t();" by hand and then press enter. In this case the end will be added automatically and will be indented correctly.

fhuebner commented 3 years ago

same behaviour in this case:

module test;
    always_comb begin
        for (int i = 0; i < NUM; i++) begin end
    end
endmodule : test

press enter with cursor places before the "end", result is:

module test;
    always_comb begin
        for (int i = 0; i < NUM; i++) begin 

  end // <- unexpected intention
    end
endmodule : test

expected:

module test;
    always_comb begin
        for (int i = 0; i < NUM; i++) begin

        end
    end
endmodule : test