EdaphicStudio / SystemVerilog

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plugin show problem with interface brackets in instantiation if defined after logic in the module. #39

Open fhuebner opened 3 years ago

fhuebner commented 3 years ago
interface test_interface;
    logic a;
    modport in (input a);
    modport out (output a);
endinterface : test_interface

module test;
    parameter NUM = 5;
    logic b;
    test_interface abc [NUM] (); //<- here shows the plugin the problem

endmodule : test

error message is: ',', ';', '=' or '[' expected, got '('

But if you move the row "logic b" to the row below the interface instantiation, there is not problem:

interface test_interface;
    logic a;
    modport in (input a);
    modport out (output a);
endinterface : test_interface

module test;
    parameter NUM = 5;

    test_interface abc [NUM] ();
    logic b;
endmodule : test