Formatting of regs does not align as expected

[EdaphicStudio]

Using 2018.2.BETA5 and when formatting the following code the result is not as expected:

Before formatting:

module foo;
    reg [11:0] a;
    reg b;
    reg [31:0] c, d,
    e;

    wire w1;
    wire [1:0] w2;
    wire [31:0] w3;
    wire w4,
    w5;
endmodule

After formatting:

module foo;
    reg [11:0] a;
    reg b;
    reg [31:0] c, d,
               e;

    wire        w1;
    wire [1:0]  w2;
    wire [31:0] w3;
    wire        w4,
                w5;
endmodule

Expected:

module foo;
    reg [11:0] a;
    reg        b;   //<- Note expected change
    reg [31:0] c, d,
               e;

    wire        w1;
    wire [1:0]  w2;
    wire [31:0] w3;
    wire        w4,
                w5;
endmodule

[EdaphicStudio]

Fixed in 2018.2.BETA6