Open farzadpanahi opened 11 months ago
the condition on 87, it only disables the Analog Outpin. This is why you'd see 12V when 0 is written to the DAC
and why do we have that condition?
and why do we have that condition?
due to the limitation of the circuit, DAC cannot produce true 0V. So we wanted to disable the Analog Out to set it to Digital ground. There should've been another line clearing the corresponding digital output state.
so this can be fixed : ) ?
so this can be fixed : ) ?
yes, I'm working on it :)
Cases to think about DAC:
Ch3~8:
1-1. DAC is written with voltage
1-2. DAC is written with 0V
1-3. Digital Out was High and DAC is written with voltage possible contention
1-4. Digital Out was Low and DAC is written with voltage
1-5. Digital Out was High and DAC is written with 0V possible contention
1-6. Digital Out was Low and DAC is written with 0V
Solutions:
1-3. AOUTx enabled is first, then DOUTx is switched OFF, this way the LOWER side FET is never activated
1-5. AOUTx is enabled first, then DOUTx is switched OFF, DAC gets written 0V, then disable AOUTx,
Ch1/2
2-1. DAC is written with voltage
2-2. DAC is written with 0V
2-3. Digital Out was High and DAC is written with voltage possible contention
2-4. Digital Out was Low and DAC is written with voltage
2-5. Digital Out was High and DAC is written with 0V possible contention
2-6. Digital Out was Low and DAC is written with 0V
2-7. PWM was enabled and DAC is written with voltage PWM can be seen for short time
2-8. PWM was enabled and DAC is written with 0V PWM can be seen for short time
Solutions:
2-3. AOUTx enabled is first, then DOUTx is switched OFF, this way the LOWER side FET is never activated
2-5. AOUTx is enabled first, then DOUTx is switched OFF, DAC gets written 0V, then disable AOUTx,
2-7. PWM_EN pin is disabled first, AOUTx is enabled
2-8. PWM_EN pin is disabled first, write 0 to DAC
DOUT:
Ch3~8:
1-1. DOUTx is written HIGH
1-2. DOUTx is written LOW
1-3. AOUTx was at some V and DOUTx is written HIGH
1-4. AOUTx was at 0V and DOUTx is written HIGH possible contention
1-5. AOUTx was at some V and DOUTx is written LOW
1-6. AOUTx was at 0V and DOUTx is written LOW
Solutions:
1-4. AOUTx is enabled, DOUTx is enabled, this will disengage the low side FET, then disable AOUTx
Ch1/2:
2-1. DOUTx is written HIGH
2-2. DOUTx is written LOW
2-3. AOUTx was at some V and DOUTx is written HIGH
2-4. AOUTx was at 0V and DOUTx is written HIGH possible contention
2-5. AOUTx was at some V and DOUTx is written LOW
2-6. AOUTx was at 0V and DOUTx is written LOW
2-7. PWM was enabled and DOUTx is written HIGH
2-8. PWM was enabled and DOUTx is written LOW
PWM:
To reproduce:
Note A-OUT 4 in this image. outputs are connected to inputs: 12V reading also verified using a voltmeter.
Logs from dev mgr:
from these logs it looks like that the voltage zero is properly set.
NOTES: