Closed iomartin closed 3 years ago
None of this is ideal... hacking together the XDMA stuff with our registers. I suspect the best we can do is just have one set of registers and eBPF engine per XDMA channel. The kernel will need to reserve an XDMA channel or eBPF engine when it starts an action.
No. The entire job should be initiated with one ioctl. The ioctl shouldn't return until the hardware has completed everything. Synchronous is fine seeing everything else is synchronous. Userspace can simply have one thread per channel/engine for parallelism.
I don't know at this point if we can enforce one eBPF engine per XDMA channel. It's of course easy to add it to the QEMU device but we don't know yet if it will fit in the FPGA. But we can have one set of registers for each eBPF engine + one for each XDMA channel.
Yes, that is a good idea.
No use having more XDMA channels than eBPF engines and vice versa. But yes one set of registers per engine.
The theory of operation currently states that command responses are written by the device into BAR0 registers. However, there are a couple of open questions:
/dev/hermesX
triggers a read on BAR0 which returns the command response of the last command. This is the simplest approach but doesn't really work if we have multiple command response register sets or multiple users./dev/hermesX
allows us to pass in the command identifier as an argument. The driver can keep a map of CID --> command response and return the right values. This can work with multiple users if the driver keeps a map per PID or includes the PID in the map key.