Open andrewgillis95 opened 3 years ago
Thanks, @andrewgillis95.
The native eBPF CPU design is looking good. I have a few questions:
Can you provide a "theory of operation" section to go along with your top-level view? It would be good to show how the system handles the steps described in the "sample execution" section here.
A few other minor points:
This is an excellent start, and I'm excited to see you and your team bring this design to life over the coming months.
@kellurs, to address your questions,
@spensicus,
Regarding the memory model, the design we had in mind was actually simpler than what I think you're proposing. I'm not sure we need the three sections of memory you are describing.
The Hermes memory is partitioned into N
program slots and M
data slots, and then we send a command to "run program X with data slot Y". Then program X has total freedom to use slot Y as it see fits (read/write anywhere). The device then only has to enforce that there are no out of bounds accesses.
Here is the updated design of the processor incorporating error handling and a simplified memory model. At the moment the newly added Controller block is quite vague in concept. It is included here to represent a system that reports the error from the CPU back to the driver, and also to represent a system of pointing the CPU to the first instruction in a program.
Just a quick clarification, stating that the Controller block is vague in concept is not quite correct. As the diagram I posted is intended to show everything from the CPU's point of view, the controller block here doesn't require much detail. The Controller block, along with the memory interface blocks, represents the interface between the CPU and the rest of the design, shown in more detail in the first diagram posted by @andrewgillis95
Below are some of the block diagrams that we are currently basing the design on. Please let us know if there are any concerns or inaccuracies, as we are still wrapping our heads around the interface, and DMA portion of things a bit.
Overall view:![image](https://user-images.githubusercontent.com/70174578/100646438-43c38800-32fb-11eb-8e81-980cedcfe671.png)
More detailed view of the CPU and predicted memory interface:![eBPF core](https://user-images.githubusercontent.com/70174578/100646692-94d37c00-32fb-11eb-8243-808e819233ae.png)