Eideticom / hdl-verifgui

A useful GUI tool for managing HDL verification.
https://eideticom.com
BSD 3-Clause "New" or "Revised" License
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Generate stubs for modules that have not been found. #4

Open davidlenfesty opened 3 years ago

davidlenfesty commented 3 years ago

Often it is useful to be able to generate stubs of modules that cannot be found for one reason or another, specifically to facilitate linting. Verilator will stop if it hits a file with a module instantiation it cannot find a source for. The two most probable cases for this are when you use a VHDL module in a (System)Verilog design, and when you're using vendor FPGA primitives.

With the current implementation of rSVParser, it would be relatively easy to generate the stub modules, based on the width and naming information available from these, however the user would need to specify the directions of each of the ports manually. There may be some room for automatically determining the directions as well, however that would be quite difficult to implement.

To integrate this nicely into the GUI, it would also be beneficial to properly create Python bindings for rSVParser, instead of calling the CLI tool directly.

A few other notes about this: