Closed reginalio closed 10 years ago
Latency is 2 cycles, clock the data in, clock the result out.
Also, I don't think rounding twice while adding zero should change the result...
above correction incorporated in commit https://github.com/EightAndAHalfTails/eee3-imgtec-fpu/commit/daca5f8e3db38ce21a7d50adc3529d4ecb3d36fd
So the new fpu does not have start, busy, done signals, is there a set clock cycles before I can read the result in the testbench? Also, accuracy requirements for 3D dot product is nwc, and it is chained in the way
round(ab+cd)+ef
. Would it be more suitable to change the fma configuration to the following?