Having problems with connecting the gateway hat to RpiZero w.

[mrobinson-opi]

I cannot figure out which pins to set for the reset script. spi and i2c are enabled.

tyro@rpiz:~/LR1302_loraWAN/LR1302_HAL/sx1302_hal/packet_forwarder $ ./reset_lgw.sh start CoreCell reset through GPIO24... SX1261 reset through GPIO24... CoreCell power enable through GPIO23... CoreCell ADC reset through GPIO32...

Packet Forwarder Version: 2.1.0 SX1302 HAL library version info Version: 2.1.0;

---

INFO: Little endian host INFO: found configuration file global_conf.json, parsing it INFO: global_conf.json does contain a JSON object named SX130x_conf, parsing SX1302 parameters INFO: com_type SPI, com_path /dev/spidev0.0, lorawan_public 1, clksrc 0, full_duplex 0 INFO: antenna_gain 0 dBi INFO: Configuring legacy timestamp INFO: Configuring Tx Gain LUT for rf_chain 0 with 16 indexes for sx1250 INFO: radio 0 enabled (type SX1250), center frequency 904300000, RSSI offset -215.399994, tx enabled 1, single input mode 0 INFO: radio 1 enabled (type SX1250), center frequency 905000000, RSSI offset -215.399994, tx enabled 0, single input mode 0 INFO: Lora multi-SF channel 0> radio 0, IF -400000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 1> radio 0, IF -200000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 2> radio 0, IF 0 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 3> radio 0, IF 200000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 4> radio 1, IF -300000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 5> radio 1, IF -100000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 6> radio 1, IF 100000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora multi-SF channel 7> radio 1, IF 300000 Hz, 125 kHz bw, SF 5 to 12 INFO: Lora std channel> radio 0, IF 300000 Hz, 500000 Hz bw, SF 8, Explicit header INFO: FSK channel 8 disabled INFO: global_conf.json does contain a JSON object named gateway_conf, parsing gateway parameters INFO: gateway MAC address is configured to BB555A0000000001 INFO: server hostname or IP address is configured to "eu1.cloud.thethings.network" INFO: upstream port is configured to "1700" INFO: downstream port is configured to "1700" INFO: downstream keep-alive interval is configured to 10 seconds INFO: statistics display interval is configured to 30 seconds INFO: upstream PUSH_DATA time-out is configured to 100 ms INFO: packets received with a valid CRC will be forwarded INFO: packets received with a CRC error will NOT be forwarded INFO: packets received with no CRC will NOT be forwarded INFO: GPS serial port path is configured to "/dev/ttyS" INFO: Reference latitude is configured to 0.000000 deg INFO: Reference longitude is configured to 0.000000 deg INFO: Reference altitude is configured to 0 meters INFO: Beaconing period is configured to 0 seconds INFO: Beaconing signal will be emitted at 869525000 Hz INFO: Beaconing datarate is set to SF9 INFO: Beaconing modulation bandwidth is set to 125000Hz INFO: Beaconing TX power is set to 14dBm INFO: Beaconing information descriptor is set to 0 INFO: global_conf.json does contain a JSON object named debug_conf, parsing debug parameters INFO: got 2 debug reference payload INFO: reference payload ID 0 is 0xCAFE1234 INFO: reference payload ID 1 is 0xCAFE2345 INFO: setting debug log file name to loragw_hal.log WARNING: [main] impossible to open /dev/ttyS for GPS sync (check permissions) CoreCell reset through GPIO24... SX1261 reset through GPIO24... CoreCell power enable through GPIO23... CoreCell ADC reset through GPIO32... Opening SPI communication interface Note: chip version is 0x00 (v0.0) ERROR: Failed to set SX1250_0 in STANDBY_RC mode ERROR: failed to setup radio 0 ERROR: [main] failed to start the concentrator

thanks

[seuros]

Did you fix it ?

[mrobinson-opi]

Yes, my reset_lgw.sh config area ended up looking like this and I plugged in the usb port to the pi.

GPIO mapping has to be adapted with HW

#

SX1302_RESET_PIN=16 # SX1302 reset SX1302_POWER_EN_PIN=4 # SX1302 power enable SX1261_RESET_PIN=24 # SX1261 reset (LBT / Spectral Scan) AD5338R_RESET_PIN=32 # AD5338R reset (full-duplex CN490 reference design)

[joestav]

@pine64noob - Which version of the LR1302 hat do you have? USB or SPI, or does the hat do both? I'm having serious difficulties getting this to work, at least with SPI. Have not tried USB yet.

[seuros]

USB is uart. It will not work.

SPI is needed.

[joestav]

I am trying to use SPI, but I'm seeing conflicting information regarding pinouts. From elecrow, this is what they list for pinouts of their HAT:

What pinouts are you using in the reset_lgw.sh file?

[seuros]

Which Kernel do you have ?

6.6.x changed the naming to something in the 5xx range. I will try to ssh into my gateway and paste the answer here.

[joestav]

@seuros Bullseye - 6.1.21-v8+

I originally started with Bookworm, but remembered there was a change to GPIO. Many issues with that distro, avoid unless you like headaches.

I feel like I'm close to getting this to work, but the pinouts for the Elecrow LR1302 HAT don't seem to follow the reference design, unless I am completely missing something. Thanks for the effort!

[seuros]

i have 6.6.25-v8+

before

SX1302_RESET_PIN=17     # SX1302 reset
SX1302_POWER_EN_PIN=18  # SX1302 power enable
SX1261_RESET_PIN=5     # SX1261 reset (LBT / Spectral Scan)
AD5338R_RESET_PIN=13    # AD5338R reset (full-duplex CN490 reference design)

after

SX1302_RESET_PIN=529     # SX1302 reset
SX1302_POWER_EN_PIN=530 # SX1302 power enable
SX1261_RESET_PIN=517     # SX1261 reset (LBT / Spectral Scan)
AD5338R_RESET_PIN=525    # AD5338R reset (full-duplex CN490 reference design)

[joestav]

@seuros Thank you for the update. The pinouts you provided above are the defaults. Are you able to get this to work with an Elecrow LR1302, or another manufacturer like Waveshare?

This is what I receive when trying to ./chip_id:

I'm lost now.

[seuros]

Did you enable SPI ?

You can reach me in discord. Then once fixed, you can post solution here.

[seuros]

@joestav any luck ?

[mrobinson-opi]

Use kernel version 5.10

[seuros]

Then enabling spi uart and using defaults will work.

[joestav]

Thanks guys, I'm using Bullseye, not 5.10. Another project is getting in the way at the moment, but I should pick this up Sat or Sunday. SPI, I2C, and serial are enabled on the Pi4 2gb host.

[seuros]

Any update.

[UpperM]

Hello config that work for me on PI ZERO WH (LR1302 SPI + HAT)

OS Info

root@raspberrypi:~# uname -a
Linux raspberrypi 6.6.31+rpt-rpi-v6 #1 Raspbian 1:6.6.31-1+rpt1 (2024-05-29) armv6l GNU/Linux

Updated reset_lgw.sh

#!/bin/sh

# GPIO mapping has to be adapted with HW
GPIO_CHIP=gpiochip0
GPIO_PIN_SX1302_RESET=17     # SX1302 reset
GPIO_PIN_SX1302_POWER_EN=18  # SX1302 power enable
GPIO_PIN_SX1261_RESET=5     # SX1261 reset (LBT / Spectral Scan)
GPIO_PIN_AD5338R_RESET=13    # AD5338R reset (full-duplex CN490 reference design)

# 100ms duration gpioset
GPIOSET="gpioset -m time -u 100000 $GPIO_CHIP"

# Check if gpioset is available
if ! command -v gpioset > /dev/null 2>&1; then
    echo "gpiod tools are not installed. Please install them first."

fi

init() {
    echo "CoreCell power enable on through GPIO$GPIO_PIN_SX1302_POWER_EN..."
    $GPIOSET $GPIO_PIN_SX1302_POWER_EN=1 2>/dev/null
}

reset() {
    echo "CoreCell reset through GPIO$GPIO_PIN_SX1302_RESET..."
    $GPIOSET $GPIO_PIN_SX1302_RESET=1 2>/dev/null
    $GPIOSET $GPIO_PIN_SX1302_RESET=0 2>/dev/null

    echo "SX1261 reset through GPIO$GPIO_PIN_SX1261_RESET..."
    $GPIOSET $GPIO_PIN_SX1261_RESET=0 2>/dev/null
    $GPIOSET $GPIO_PIN_SX1261_RESET=1 2>/dev/null

    echo "CoreCell ADC reset through GPIO$GPIO_PIN_AD5338R_RESET..."
    $GPIOSET $GPIO_PIN_AD5338R_RESET=0 2>/dev/null
    $GPIOSET $GPIO_PIN_AD5338R_RESET=1 2>/dev/null
}

term() {
    echo "CoreCell power enable off through GPIO$GPIO_PIN_SX1302_POWER_EN..."
    $GPIOSET $GPIO_PIN_SX1302_POWER_EN=0 2>/dev/null
}

case "$1" in
    start)
    init
    reset
    ;;
    stop)
    reset
    term
    ;;
    *)
    echo "Usage: $0 {start|stop}"
    exit 1
    ;;
esac

exit 0

Result

root@raspberrypi:/LR1302_loraWAN/LR1302_HAL/sx1302_hal# ./reset_lgw.sh start
CoreCell power enable on through GPIO18...
CoreCell reset through GPIO17...
SX1261 reset through GPIO5...
CoreCell ADC reset through GPIO13...

root@raspberrypi:/LR1302_loraWAN/LR1302_HAL/sx1302_hal# packet_forwarder/lora_pkt_fwd -c packet_forwarder/global_conf.json.sx1250.EU868
*** Packet Forwarder ***
Version: 2.1.0
*** SX1302 HAL library version info ***
Version: 2.1.0;
***
INFO: Little endian host
INFO: found configuration file packet_forwarder/global_conf.json.sx1250.EU868, parsing it
INFO: packet_forwarder/global_conf.json.sx1250.EU868 does contain a JSON object named SX130x_conf, parsing SX1302 parameters
INFO: com_type SPI, com_path /dev/spidev0.0, lorawan_public 0, clksrc 0, full_duplex 0
INFO: antenna_gain 0 dBi
INFO: Configuring legacy timestamp
INFO: Configuring Tx Gain LUT for rf_chain 0 with 16 indexes for sx1250
INFO: radio 0 enabled (type SX1250), center frequency 867500000, RSSI offset -215.399994, tx enabled 1, single input mode 0
INFO: radio 1 enabled (type SX1250), center frequency 868500000, RSSI offset -215.399994, tx enabled 0, single input mode 0
INFO: Lora multi-SF channel 0>  radio 1, IF -400000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 1>  radio 1, IF -200000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 2>  radio 1, IF 0 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 3>  radio 0, IF -400000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 4>  radio 0, IF -200000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 5>  radio 0, IF 0 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 6>  radio 0, IF 200000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora multi-SF channel 7>  radio 0, IF 400000 Hz, 125 kHz bw, SF 5 to 12
INFO: Lora std channel> radio 1, IF -200000 Hz, 250000 Hz bw, SF 7, Explicit header
INFO: FSK channel> radio 1, IF 300000 Hz, 125000 Hz bw, 50000 bps datarate
INFO: packet_forwarder/global_conf.json.sx1250.EU868 does contain a JSON object named gateway_conf, parsing gateway parameters
INFO: gateway MAC address is configured to XXXXXXXXXXXX
INFO: server hostname or IP address is configured to "192.168.1.147"
INFO: upstream port is configured to "1700"
INFO: downstream port is configured to "1700"
INFO: downstream keep-alive interval is configured to 10 seconds
INFO: statistics display interval is configured to 30 seconds
INFO: upstream PUSH_DATA time-out is configured to 100 ms
INFO: packets received with a valid CRC will be forwarded
INFO: packets received with a CRC error will NOT be forwarded
INFO: packets received with no CRC will NOT be forwarded
INFO: GPS serial port path is configured to "/dev/ttyS"
INFO: Reference latitude is configured to 0.000000 deg
INFO: Reference longitude is configured to 0.000000 deg
INFO: Reference altitude is configured to 0 meters
INFO: Beaconing period is configured to 0 seconds
INFO: Beaconing signal will be emitted at 869525000 Hz
INFO: Beaconing datarate is set to SF9
INFO: Beaconing modulation bandwidth is set to 125000Hz
INFO: Beaconing TX power is set to 14dBm
INFO: Beaconing information descriptor is set to 0
INFO: packet_forwarder/global_conf.json.sx1250.EU868 does contain a JSON object named debug_conf, parsing debug parameters
INFO: got 2 debug reference payload
INFO: reference payload ID 0 is 0xCAFE1234
INFO: reference payload ID 1 is 0xCAFE2345
INFO: setting debug log file name to loragw_hal.log
WARNING: [main] impossible to open /dev/ttyS for GPS sync (check permissions)
CoreCell power enable on through GPIO18...
CoreCell reset through GPIO17...
SX1261 reset through GPIO5...
CoreCell ADC reset through GPIO13...
Opening SPI communication interface
Note: chip version is 0x10 (v1.0)
INFO: using legacy timestamp
INFO: LoRa Service modem: configuring preamble size to 8 symbols
ARB: dual demodulation disabled for all SF
INFO: found temperature sensor on port 0x39
INFO: [main] concentrator started, packet can now be received
INFO: concentrator EUI: 0x0016c001f1056e0f
INFO: [down] PULL_ACK received in 3 ms

Still need to fix GPS

[seuros]

@UpperM Disable uart logger from the bootcmd and check your config /dev/ttyS is not a valid port.

[UpperM]

It was my config that try to use /dev/ttyS but the correct is /dev/ttyS0 its working now :)