[2 MHz] TMS320F Code preperation

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squeezing all the bits to the limits

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We had 200 clock cycles in single 1 MHz timer,

• 200 MHz / 1 MHz = 200

our aim is to update the duty cycle within this 200 cycle

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After turning on the optimization for main.c the full timer interrupt routine takes about 68 cycles including sine calculation, counting and updating the duty cycle registers.

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It has been able to operate with 1 MHz switching frequency with 10 kHz increments (it was presumed to be 5 kHz) and 87.5 kHz fundamental with 50 Hz increments.

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The output pwm is jittery since the sine calculations are not synchronized (I guess), but the FFT of the output seems to be accurrate in representing 87.5 kHz and 1.07 MHz.