wordimont
commented
1 year ago "my question is if is possible to write the registers of the .hv from a vhdl code." It's not clear to me how you have the Replay block connected. Is your block driving the ctrlport interface on axis_replay? If that's the case, then yes, you can write the registers from your VHDL code following the CtrlPort protocol. The registers are really intended to be written by software running on a host computer or the Zynq's ARM CPU. You can look at the SV testbench and the C++ block controller to see how the registers are supposed to be used.
"I would like to know if when the replay block is reset, the replay (the output) is affected" Yes, reset would stop anything in progress. If you want to use the block as a FIFO, then I suggest you use the FIFO block instead of the Replay block. It is much simpler if all you want is FIFO behavior.
I think these questions are better suited for the mailing list. Since this isn't an issue/bug in the UHD code, I'll close this issue.
Issue Description
I'm trying to use the Replay block that RFNOC provides however i have some doubts about the connections. My idea is: I have a Custom IP that recieves the data. After some time, an event occurs and i need to store the input data in the RAM. I have connected the AXI Stream Interface between the Custom and the axis_replay, futhermore the setting bus. When the event appears, i restart the recording with REG_REC_RESTART. However, my question is if is possible to write the registers of the .hv from a vhdl code. I've seen how tb do it but it is a .sv file and i would like not to change my vhd file. On the other hand, i assumed that, to replay the data, i have to set the REG_PLAY_CMD.
Also, I would like to know if when the replay block is reset, the replay (the output) is affected, as I want to use this block as a continuous FIFO. I have checked that there is another block as fifo_ram but I don't understand how the read and write is initiated.
The scheme I would like would be more or less like this (The scheme I would like would be more or less like:
| CUSTOM | <-------- axi stream interface -------- > | REPLAY | <----------- Memory Interface --------> Axi DMA Master | IP | <-------- Setting bus -------- > | |
Setup Details
Ubuntu 20.04.4 LTS 64-bit UHD 4 USRP E320 or X310 Connection to the device is via Ethernet.
Expected Behavior
Connection between custom block (with a little controler) and the replay block.
Actual Behaviour
No connection between both.
Steps to reproduce the problem
Add the custom RFNOC block. Connect with RFNOC Replay Generate the image.
Additional Information