Closed ryanvolz closed 4 months ago
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@ryanvolz FYI we're reviewing this internally. I think this change is OK.
(Note: In order to not repeat the mistake of finding a similar issue in another part of the codebase ~8 years later =P, I checked the RFNOC usrp3's DDC to see what it does. Thankfully, it doesn't have this problem since it uses a wider multiplier and thus avoids the truncation.)
Oh, and we very much appreciate this ^^^ :+1:
Pull Request Details
Description
Currently, the non-RFNOC usrp3 (i.e. B2xx) DDC code truncates to 18 bits from 24 bits after applying the halfband filters and before applying a scaling and final rounding. This truncation introduces a DC bias that is noticeable with small signal levels (or lots of integration), especially with high decimation rates. Changing the truncation to a rounding removes the DC bias.
This is essentially a forward port of a similar prior fix to the usrp2 DDC chain: https://github.com/EttusResearch/fpga/pull/4. (Note: In order to not repeat the mistake of finding a similar issue in another part of the codebase ~8 years later =P, I checked the RFNOC usrp3's DDC to see what it does. Thankfully, it doesn't have this problem since it uses a wider multiplier and thus avoids the truncation.)
Related Issue
Which devices/areas does this affect?
USRP3-based non-RFNOC devices, i.e. B2xx and B2xxmini
Testing Done
I tested this with a B200mini using GNU Radio. Without the radio connected to anything, I tuned with an LO offset of 1 MHz, gain of 0, and high decimation factor (master clock of 40e6, sample rate of 200e3). Using the stock fpga, a DC bias is present:
Using this modification, the DC bias is gone:
Checklist