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The USRP™ Hardware Driver Repository
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FPGA build fails under Cygwin (no such variable) #738

Closed feyzaozdemir closed 3 months ago

feyzaozdemir commented 3 months ago

Issue Description

I followed https://files.ettus.com/manual/md_usrp3_build_instructions.html . More than 7 hours have passed after running make X410_X1_100 GUI=1 command in cygwin. I know some builds take a long time but Is it taking this long? Is this normal? What must I do?

Setup Details

My OS is Windows 10, I installed Vivado 2021.1 and added patch AR76780 as in manual. I installed Cygwin and packages. Then I followed the build instructions from cygwin.

Expected Behavior

Reaching the FPGA project in usrpx410 at the end of the build. If the build duration is normal, can I also get information about the accuracy of the method? If I cant reach the project after building, then how can i get the project?

Actual Behavior

BUILDER: Releasing IP location: /cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400/build-ip/xczu28drffvg IP build for X410_IP DONE . . . make[1]: Leaving directory '/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400' mkdir -p ./build tools/parse_versions_for_dts.py \ --input regmap/x410/versioning_regs_regmap_utils.vh \ --output dts/x410-version-info.dtsi \ --components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m cc -o build/usrp_x410_fpga_X1_100.dts -C -E -I dts -nostdinc -undef -x assembler-with-cpp -DDTS \ $(python3 tools/get_dts_input.py --target build/usrp_x410_fpga_X1_100.dts) make -f Makefile.x4xx.inc bin NAME=X410_X1_100 ARCH=zynquplusRFSOC PART_ID=xczu28dr/ffvg1517/-1/e BUILD_SEED RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*1 DRAM_W=64 X410=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=x41 make[1]: Entering directory '/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400' BUILDER: Checking tools...

wordimont commented 3 months ago

You requested the GUI. Did the Vivado GUI open? If you build it in the GUI then the GUI will stay open until you close it and you won't really get any information in the terminal. Perhaps the GUI is waiting for you. If the GUI isn't opening, you could try building it without the GUI=1 option.

Build time depends on your computer, if it has to build the IP or not, and which USRP target. I would guess an hour to build that particular target if you already built the IP.

feyzaozdemir commented 3 months ago

Yes, Vivado GUI opened but nothing happened at GUI, just opening page. Do I just need to close the GUI? Is there any difference building with GUI or opening GUI after building?

wordimont commented 3 months ago

Make sure the Tcl console was open in the GUI and see if there was any output. You can also check the build and build-X410_X1_100 directories to see if any files were produced. If not, then I would guess this problem is related to running under Cygwin. See if it works without the GUI=1 option. You should see lots of output to the terminal if it's working.

Building in the GUI and in the terminal should be the same. It's just running Vivado either way. People use the GUI option if they want to use the GUI at the end of the build while the design is still in memory. But you can basically do the same thing by loading the final checkpoint in Vivado after the build is done in the terminal.

feyzaozdemir commented 3 months ago

After canceling the process, I opened cygwin again and I entered the following into the terminal: source setupenv.sh make cleanall make x410_X1_100

There was no problem with IP generation. And then this happened:

BUILDER: Releasing IP location: /cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/dds_sin_cos_lut_only IP build for X410_IP DONE . . . make[1]: Leaving directory '/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400' mkdir -p ./build tools/parse_versions_for_dts.py \ --input regmap/x410/versioning_regs_regmap_utils.vh \ --output dts/x410-version-info.dtsi \ --components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m cc -o build/usrp_x410_fpga_X1_100.dts -C -E -I dts -nostdinc -undef -x assembler-with-cpp -DDTS \ $(python3 tools/get_dts_input.py --target build/usrp_x410_fpga_X1_100.dts) make -f Makefile.x4xx.inc bin NAME=X410_X1_100 ARCH=zynquplusRFSOC PART_ID=xczu28dr/ffvg1517/-1/e BUILD_SEED=0 QSFP0_0=2 RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=41 DRAM_W=64 X410=1 TOP_MODULE=x4xx EXTRA_DEFS=" BUILD_SEED=0 QSFP0_0=2 RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=41 DRAM_W=64 X410=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400/x410_200_static_router.hex INCR_BUILD=0 make[1]: Entering directory '/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400' BUILDER: Checking tools...

======================================================== Warnings: 0 Critical Warnings: 0 Errors: 0

make[1]: [Makefile.x4xx.inc:232: bin] Error 1 make[1]: Leaving directory '/cygdrive/e/v21_projects/uhd-master/fpga/usrp3/top/x400' make: [Makefile:169: X410_X1_100] Error 2

I checked; make[1]: *** [Makefile.x4xx.inc:232: bin] Error 1, line 228-232 ->

DESIGN_SRCS and VERILOG_DEFS must be defined

bin: .prereqs @ echo "Printing MB_XDC:: $(MB_XDC)" @ echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS)" $ (call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))

make: *** [Makefile:169: X410_X1_100] Error 2, line 168-170 -> X410_X1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_100.dts $ (call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,X1_100)

wordimont commented 3 months ago

Can you open build-X410_X1_100/build.log and see if there's an error message or warning in there?

Which UHD version branch/commit are you building from?

feyzaozdemir commented 3 months ago

I'm building from master branch.

here is the log file, except for comment lines

no such variable (read trace on "::env(VIV_SAVE)") invoked from within "variable g_project_save $::env(VIV_SAVE)" (in namespace eval "::vivado_utils" script line 12) invoked from within "namespace eval ::vivado_utils {

Export commands

namespace export \
    initialize_project \
    synthesize_design \
    check_de..."
(file "E:/v21_projects/uhd-master/fpga/usrp3/tools/scripts/viv_utils.tcl" line 8)

while executing

"source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl" (file "E:/v21_projects/uhd-master/fpga/usrp3/top/x400/build_x4xx.tcl" line 7) INFO: [Common 17-206] Exiting Vivado at Fri Mar 29 08:18:06 2024...

wordimont commented 3 months ago

Try building off of the latest release branch (UHD-4.6). I don't recommend building off of master unless you have a specific reason. I'll have to reproduce this on Cygwin to see what's going on. It looks like some variables aren't being defined.

feyzaozdemir commented 3 months ago

I started building, looks like no problems so far. Let's not close the issue until monday so If there is a problem, I will inform you.

feyzaozdemir commented 3 months ago

Build done without error. I was expecting .xpr file and seeing all of project files. There are only .rpt and .dcp files. How can I get the whole project? I saw uhd/fpga/usrp3/lib directory has all files but i need the whole system with block design. I want to examine and understand the entire project and make my own additions.

wordimont commented 3 months ago

USRP builds use Vivado's non-project mode. For a quick summary see the FAQ here: https://kb.ettus.com/RFNoC_Frequently_Asked_Questions#How_do_I_create_a_Vivado_project_for_my_FPGA_build.3F

wordimont commented 3 months ago

I found the cause of the original issue on master and created a pull request with a fix. There was a variable (VIV_SAVE) set to an empty string, which works fine under Linux but for some reason it doesn't work under Cygwin/Windows. Turns out it was empty because we were pulling the value from the wrong variable.

feyzaozdemir commented 3 months ago

Thank you for help.