mbr0wn
commented
4 days ago Hi @NIDHIPANDA, this question is a pure support question, and this is not a support forum. Please use other media for support.
You probably don't need to access any ZPU registers.
I am having USRP X300 device with following tool versions:
Vivado 2021.1 - AR76780n, GNU radio version - v3.11.0.0git-820-g2adbd4ea UHD version - UHD_4.7.0.0-84-gbdada1ed
I have created FPGA image file for HG mode using "rfnoc_image_builder". It includes radio0/1, DDC0/1, DUC0/1 and replay module by default. I tested it on hardware also. It works fine. Now I want to add different RFNoC block in my design. On following "https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0%22" guide, I am trying to add FFT IP. This gives multi-driven clock error in implementation. Is it because this guide is for X310 board. Can anyone guide me the process of editing of ".yml script "to add FFT block for USRP X300. I have attached my .yml script for reference.
Another question is about register map. Can anyone explain where can I find register map for USRP X300. Where can I find addresses I need to configure for different variable registers using softcore ZPU.
/////// YML script file to add FFT RFNOC into design. //////////////////////
General parameters
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file copyright: >- # Copyright information used in file headers Copyright 2023 Ettus Research, a National Instruments Brand license: >- # License information used in file headers SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this image device: 'x310' image_core_name: 'usrp_x310_fpga_HG' # This is used for the bitfile, DTS, and report default_target: 'X310_HG' inherit:
A list of all stream endpoints in design
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stream_endpoints: ep0: # Stream endpoint name buff_size: 32768 # Ingress buffer size for data ep1: buff_size: 0 ep2: buff_size: 32768 ep3: buff_size: 0 ep4: buff_size: 4096 ctrl: False data: True ep5: buff_size: 4096 ctrl: False data: True
ep_fft: # The name can be incremented from previous SEP ctrl: False # Only the first SEP needs control traffic data: True # We do want to pass data through this SEP buff_size: 32768 # Ingress buffer size for data
A list of all NoC blocks in design
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noc_blocks: replay0: block_desc: 'replay.yml' parameters: NUM_PORTS: 2 MEM_DATA_W: 64 MEM_ADDR_W: 30 priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
fft0: # FFT block name block_desc: 'fft_1x64.yml' # Block YAML descriptor file parameters: # Specify any Verilog module parameters (optional) EN_FFT_SHIFT: 1
A list of all static connections in design
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Format: A list of connection maps (list of key-value pairs) with the following keys
- srcblk = Source block to connect
- srcport = Port on the source block to connect
- dstblk = Destination block to connect
- dstport = Port on the destination block to connect
connections:
Replay Connections
BSP Connections
A list of all clock domain connections in design
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Format: A list of connection maps (list of key-value pairs) with the following keys
- srcblk = Source block to connect (Always "device")
- srcport = Clock domain on the source block to connect
- dstblk = Destination block to connect
- dstport = Clock domain on the destination block to connect
clk_domains: