Error in parsing the last Output in a module due to HDL Parse

[Eyantra698Sumanto]

Description

Error in parsing the last Output in a module due to HDL Parse

module dut(

       input clk,rst,
       output reg [2:0]light_S1,
       output reg [2:0]light_S2,
       output reg [2:0]light_S3,
       output reg [2:0]light_S4,
       );

Parsing the above code gives number of ports for S4 as 1.

Steps to Reproduce

Pass the code through the NgVeri(HDLparse), it will give the number of ports of S4 in the eSim terminal as 1.

Expected Behavior

The number of Ports of S4 need to be 3.

Screenshots

Version and OS

• eSim -2.2
• OS: Linux, Windows

Additional Context

Tempory fix is to have the module declaration in the following format:

module DUT(

       output reg [2:0]light_S1,
       output reg [2:0]light_S2,
       output reg [2:0]light_S3,
       output reg [2:0]light_S4,
       input clk,rst
       );