The FPGA design is located in FPGA/sdram_ctrl folder
I design a state machine sdram_top.sv that writes 15 times and than reads 15 times.
In simulation the state machine works fine but in practice we cant read the data (see in signal tap).
You can see the addresses works alright (I showed a small portion of them 0x000A, 0x000B...
The FPGA design is located in
FPGA/sdram_ctrlfolder I design a state machinesdram_top.svthat writes 15 times and than reads 15 times. In simulation the state machine works fine but in practice we cant read the data (see in signal tap). You can see the addresses works alright (I showed a small portion of them 0x000A, 0x000B...The reads are not working