FPGA-MAFIA / fpga_mafia

Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
MIT License
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[big_core][defines]#600: Add VGA CounterX and CounterY to CR space for timing #625

Closed NoamRahat closed 5 months ago

NoamRahat commented 5 months ago

This commit introduces changes to synchronize content updates with the monitor's refresh cycle. Specifically, it adds the VGA CounterX and CounterY to the CR (Control Register) space, making them accessible from timing.

To achieve synchronization with the monitor's refresh rate and avoid flickering, it's crucial to update the display content during the vertical retrace period. By exposing the CounterY, we can determine the display cycle's current position and ensure content updates occur at the correct time. Previously, ensuring synchronization relied on vertical synchronization (V-Sync) methods, especially during the vertical retrace period for CRT displays. With the introduction of CounterY, we gain insight into the display cycle, enabling precise content updates at the appropriate times. WhatsApp Image 2024-04-18 at 17 25 08

Changes Made:

These modifications set the groundwork for future features and software enhancements within the project.

Hierarchy of Changes:

  1. Definitions added in 'big_core_defines.h'.
  2. Integration in 'big_core_cr_mem.sv' and 'big_core_mem_wrap.sv'.
  3. Output inclusion in 'big_core_vga_ctrl.sv'.
  4. Structure definition in 'big_core_pkg.sv'.

These changes enhance synchronization capabilities, laying the foundation for further developments in the project.

Signed-off-by: NoamRahat noamrht@gmail.com

amichai-bd commented 5 months ago

@NoamRahat 1) Please create a test for this new "feature" you added.. create a test that can read the CR value and print it to display - i sent you an example via watsapp the other week 2) Make sure the Sanity level0 and level2 (you can run this command: ./scripts/sanity_check.py -yml mafia_level2 -dut big_core Or this: ./scripts/sanity_check.py -yml mafia_level0 -dut big_core At minimum: run 1 test and as a "fast turn around" design cycle - simply use this command: python build.py -dut big_core -test alive -app -hw -sim -pp

amichai-bd commented 5 months ago

Please review and fix image

NoamRahat commented 5 months ago

image image does this make sense? seam's it's not updating

NoamRahat commented 5 months ago

on my machine I pass the sanity_check: image

NoamRahat commented 5 months ago

@amichai-bd

amichai-bd commented 5 months ago

Great job! Please link the relevant issue. (Press on the development button on this page)

I will not merge this into main yet. Waiting to see yakov version of this fix