Sdram controler for read/write 8 length bursts

[roman012285]

• The FPGA design of the controller is located at /FPGA/sdram_full
• The name of the controller it self is located at source/mem_ss/sdram_ctrl_bursts

NOTE - I have added many files that will be removed when the full memory sub system will work. That includes some FPGA folders and some *.vh files inside source/mem_ss folder

For example

• Write to random adress 0x0018
  • Read from that address

• Read/Write data and address can be seen here