CPU IO Tile

[ogris]

Hello, I'm looking to extend an open-source RISC-V core with an internally connected FPGA coprocessor. To realize my project, I require a tile with multiple input or output ports. Unfortunately, the example in the documentation using CPU_IO isn't functioning, and all references to CPU_IO have been removed from the Tile folder.

Could you please give me a hint on which tile I should use and how to modify it to achieve a similar result? Thank you in advance for your efforts. With best regards, Max

[KelvinChung2000]

You can try to modify the IO tile to achieve what you want. fabric_files/FABulous_project_template_vhdl/Tile/CPU_IO/ and fabric_files/FABulous_project_template_verilog/Tile/W_IO/IO_1_bidirectional_frame_config_pass.v are some examples of how you can create the IO you are looking for.

All external IO is defined by using (* FABulous, EXTERNAL *) keyword, and you can create your custom primitive to provide the width you are looking for.

But depending on how deeply you are coupling your FPGA fabric with the CPU pipeline and what you are using the FPGA fabric for, you might be able to just wire your CPU IO to the original IO, similar to how we perform testing. You can look into the fabric_files/FABulous_project_template_verilog/Test/fabulous_tb.v and instantiate a fabric similarly.