Missing documentation of MID wires

[IAmMarcelJung]

It seems that there is no documentation for MID wires. The documentation could include an image visualizing the feature with a short explanation.

[dirk-koch]

There is not really anything magic with the MID wires. They are double wires that you can access half-way through. They are modeled as two cascaded single wires. MID wires had been heavily used in older Xilinx devices.

There is however something deeper here: MID wires is one trick to balance metallization congestion towards core cell area....

[IAmMarcelJung]

There may not be anything magic with them, but someone how is unfamiliar with the terminology (like I was) might still not know what they do, although it is quite simple. Maybe a short description might also do the trick and the image is not needed?