search

FPGA-Research-Manchester / FABulous

Fabric generator and CAD tools
https://fabulous.readthedocs.io/en/latest/
Apache License 2.0
142 stars 31 forks source link

Missing configuration for CPU_IO #160

Open mole99 opened 4 months ago

mole99 commented 4 months ago

The CPU_IO tile is currently not available for Verilog and misses configurations in VHDL.

Instead of removing this tile, it would be nice if its functionality could be restored.

dirk-koch commented 3 months ago

While our I/O stuff works, I am not super happy with how it is used. Meaning, its not good to provide different I/O BELs whenever something minor changes. I want this more like something that you can specify an I/O BEL in the form #in, #out, #inout, #config_bits with a name prefix and fundamentally that's it. Of course if you have other requirements, you will still be able to provide BEL I/Os as RTL code... There is somebody working on it right now.

mole99 commented 3 months ago

Hello Dirk, That sounds like a good solution. Great to hear that somebody is already working on it. Can't wait to try it out 👍️