Add documentation of MID wires

[IAmMarcelJung]

This would resolve #140. The image is a screenshot taken from inside FABulator. Although it might not be the best visualization due to the thin wires, it's something and maybe could be replaced in the future. Either by an updated version if thicker lines are supported or if somebody wants to draw an image themselves, this would also to the trick.

The explanation might also be a bit flawed but this is as far as I understood it from explanation by @dirk-koch and the visualization of FABulator. Also I'm not sure if I inserted the content into the correct place in the text.

As always, any feedback is therefore highly appreciated!

[dirk-koch]

Hi folks, I would leave the mid ports. The reason is that Xilinx used a lot so called MID ports in older FPGAs. For instance Double wired had a MID port after one switch matrix and hex wires after 3 switch matrices respectively. In FABulous, this is simply modeled by concatenating two shorter segments (two singles for a double or two triple for a hex wire). So the E2BEGb is then the begin port of the second single leg forming a double with a MID port. I hope this is not too confusing. There is some documentation on this in the readthedocs. The same method can be used to model the diagonal routing available in Virtex-V (if somebody wants to model that architecture in FABulous).

[IAmMarcelJung]

Hi folks, I would leave the mid ports.

@dirk-koch We are not planning to remove the MID ports but rather wanted to add some documentation for them, since not everyone might be as familar with the Xilinx stuff as you are ;D With that said, do you agree with the short description that was added? Or is there anything you would improve or add?

[TaoBi22]

@IAmMarcelJung I got the go-ahead from Dirk so I'll get this merged!

[IAmMarcelJung]

Nice, thanks!