Synthesis of VHDL

[Biswajitks1]

This pull request introduces the use of the GHDL plugin in Yosys to synthesize VHDL files.The top_wrapper was converted to vhdl and tried to use ghdl but it was unable to interpret the attributes(constraints) so by using yosys read_verilog command the top_wrapper.v can be used.

[KelvinChung2000]

Please add some documentation about synthesis with VHDL that will require a GHDL Yosys extension and how it should get set up.

[Biswajitks1]

I will add documentation about that and also correct the error,thank you.

[Biswajitks1]

Sorry I messed soemthing up so creating a new branch and will create a pull request by adding documentation and correcting errors.