Open hhnurr opened 2 weeks ago
X
is usually an uninitialised value. Signals that contain END
are inputs, and BEG
are outputs. Tracing at what point the END
is X
might help. So, for example, the X3_Y0 N_term N1END will be driven by X3_Y1
The default N_term offers no IO but more routing twists.
Hi, I'm running the demo project, but I've noticed something confusing. While checking the waveforms, I see various 'X' values appearing in the simulation. Although these 'X's don't seem to affect the functionality of the FPGA in the demo project, I’m encountering a similar issue after adding North and South IOs to my architecture. In my case, the 'X's propagate from the switch matrix to the output, impacting functionality. Could you explain the reason behind the 'X' values in the demo project? This information might help me troubleshoot my issue more effectively. I've attached a screenshot of my waveforms for reference. Thank you!