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FPGA-Research-Manchester / FABulous

Fabric generator and CAD tools
https://fabulous.readthedocs.io/en/latest/
Apache License 2.0
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Improve VPR output instantiation #41

Open TaoBi22 opened 2 years ago

TaoBi22 commented 2 years ago

When VPR takes in a circuit in BLIF format, it names blocks internally after the first net they drive. This name is then what we use in the constraints file. For BELs that drive something this is fine, but for output BELs (e.g. OutPasses) there is no net to derive a name from. Instead, VPR enumerates them - the first such BEL is unnamed_subckt0, the second is unnamed_subckt1 and so on.

When we generate constraints for the VPR flow, we predict this enumeration, for example adding the atom unnamed_subckt0 to the region for the very first OutPass found in the fabric model (from fabric.csv). This is far from ideal though! If someone isn't using the first few OutPasses and removes them from the file then the first one they instantiate becomes unnamed_subckt0, constraining it to the position of the first one found in the fabric.csv file.

I'm not too sure what the best way to tackle this is. Ideally it would be something that we can fix without modifications to upstream VPR, since it's a pretty niche use-case, but nothing stands out to me as a potential workaround. Maybe some way to 'trick' VPR into giving the BELs a name? But I'm not too sure how we could do that without diverging from the appropriate subckt definition. Very open to any suggestions!

IAmMarcelJung commented 3 weeks ago

I guess this is outdated due to #221 @KelvinChung2000.