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FPGAwars / apio

:seedling: Open source ecosystem for open FPGA boards
https://github.com/FPGAwars/apio/wiki
GNU General Public License v2.0
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VHDL design entry via GHDL Yosys plugin #233

Open PPlinux opened 3 years ago

PPlinux commented 3 years ago

Dear,

is there already support for VHDL design entry via GHDL Yosys plugin ?

Hoping to receive a positive reaction, I remain,

Greetings,

Patrick Pelgrims

Obijuan commented 3 years ago

Not yet. It is on the roadmap, but we still have not started it