Please support multiple test benches in the same directory.

[zapta]

In my project i have mutliple verilog files foo.v, bar.v, and so on, and each has a testbench foor_tb.v, bar_tb.v, etc. When I try to run 'apio sim' it complains that "more than one testbenches used" and pick one arbitrarily.

Please extend 'apio sim' to accept the name of the testbench to run. Having multiple .v files with a test bench for each is a very common practice.

EDIT: Looking at the code below I think that adding to apio sim an --testbench flag will allow to select the testbench from that value and remove all the other testbenches from src_sim.

list_scanner = env.Scanner(function=list_files_scan)

# -- Get a list of all the verilog files in the src folfer, in ASCII, with
# -- the full path. All these files are used for the simulation
v_nodes = Glob('*.v')
src_sim = [str(f) for f in v_nodes]

# --------- Get the Testbench file (there should be only 1)
# -- Create a list with all the files finished in _tb.v. It should contain
# -- the test bench
list_tb = [f for f in src_sim if f[-5:].upper() == '_TB.V']

if len(list_tb) > 1:
    print('Warning: more than one testbenches used')

# -- Error checking
try:
    testbench = list_tb[0]

# -- there is no testbench
except IndexError:
    testbench = None

[zapta]

Hi @Obijuan, can I send you a PR for this? It adds an optional --testbench flag to the sim command. E.g.

apio --teshbench my_module_tb.v

I have a working version with a patched 0.8.4. The key patch is in SConstruct and looks like this:

# -- Get a list of all the verilog files in the src folfer, in ASCII, with
# -- the full path. All these files are used for the simulation
v_nodes = Glob('*.v')
v_files = [str(f) for f in v_nodes]

# Create lists of module and testbench files. Test benches are assumed
# to end with '_tb.v', case insensitive.
src_sim = [f for f in v_files if f[-5:].upper() != '_TB.V']
list_tb = [f for f in v_files if f[-5:].upper() == '_TB.V']

# Handle the testbench selection, if any. 
testbench = None

if TESTBENCH:
  testbench = TESTBENCH
else:
  if len(list_tb) > 1:
    print('Warning: more than one testbench found.')
  if len(list_tb) > 0:
    testbench = list_tb[0]

# Add the testbench to the list of compiled files.
if testbench:
  src_sim.append(testbench)

[Obijuan]

Hi @zapta!

Yes, you can send the PR, for sure. Please, send it to the Develop branch

[zapta]

Thanks @Obijuan. I sent you this PR https://github.com/FPGAwars/apio/pull/341

[Obijuan]

Hi @zapta! I think that this issue is fixed with your PR. Please, close this issue if everything is working as expected. Thank you very much for all your contributions

[zapta]

Closing. The sim command now has a flag to select the testbench to simulate.

$ apio sim --help
Usage: apio sim [OPTIONS]

  Launch the verilog simulation.

Options:
  -p, --project-dir path     Set the target directory for the project.
  -t, --testbench testbench  Specify the testbench file to simulate.
  -h, --help                 Show this message and exit.

[375432636]

it seems like not support yet. is that anything error about my opreation? i'm using the apio version downloaded by pip. should i use other version like the test/dev version?

PS Documents\project\fpga\step_baseboard_v40_v2> apio sim --help
Usage: apio sim [OPTIONS]

  Launch the verilog simulation.

Options:
  -p, --project-dir path  Set the target directory for the project.
  --help                  Show this message and exit.
PS Documents\project\fpga\step_baseboard_v40_v2> apio sim -t    
Usage: apio sim [OPTIONS]
Try 'apio sim --help' for help.

Error: No such option: -t
PS Documents\project\fpga\step_baseboard_v40_v2> apio --version
apio, version 0.8.4
PS Documents\project\fpga\step_baseboard_v40_v2>

[zapta]

That was added post 0.8.4 so I presume it will come with the upcoming 0.9.

https://pypi.org/project/apio/#history