FPGAwars / apio

:seedling: Open source ecosystem for open FPGA boards
https://github.com/FPGAwars/apio/wiki
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Extended the apio clean command to delete all the .out and .vcd files. #342

Closed zapta closed 4 months ago

zapta commented 4 months ago

With this change. the 'apio clean' commands now deletes also all the .out and .vcd files it find. The motivation is the immediate motivation is new multi testbench approach but it's useful also for a general cleanup of orphan artifacts, for example, when a testbnech is renamed leaving behind artifacts with the old name.

Obijuan commented 4 months ago

Thanks! 😀️

zapta commented 4 months ago

I am working on one more PR.

In case you are planning a release, please wait a day or two for it.

Thanks

On Tue, Feb 20, 2024 at 12:03 AM Juan Gonzalez-Gomez < @.***> wrote:

Thanks! 😀️

— Reply to this email directly, view it on GitHub https://github.com/FPGAwars/apio/pull/342#issuecomment-1953665128, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAQVMQJXONL6DGWMNY24OUTYURKERAVCNFSM6AAAAABDQUNKEKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSNJTGY3DKMJSHA . You are receiving this because you authored the thread.Message ID: @.***>

Obijuan commented 4 months ago

Do not worry. I am planning a release, but i still need to stabilize the current version: i have to update all the examples and test on the different boards i have. It will take me some weeks

zapta commented 4 months ago

Just sent you PR https://github.com/FPGAwars/apio/pull/343, please take a look.

Regarding the testbenches, do you think apio lint/verify should also process testbenches? Currently they do just module files. I can make the change if needed.

Also when I run apio lint I get the error below. Any plans to add it as an auto install apio resource?

sh: verilator: command not found

scons: *** [hardware] Error 127

On Tue, Feb 20, 2024 at 10:10 AM Juan Gonzalez-Gomez < @.***> wrote:

Do not worry. I am planning a release, but i still need to stabilize the current version: i have to update all the examples and test on the different boards i have. It will take me some weeks

— Reply to this email directly, view it on GitHub https://github.com/FPGAwars/apio/pull/342#issuecomment-1954792409, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAQVMQKOHFG3GDYQ47BG5PDYUTRJNAVCNFSM6AAAAABDQUNKEKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSNJUG44TENBQHE . You are receiving this because you authored the thread.Message ID: @.***>

Obijuan commented 4 months ago

I think is ok to verify/lint also the testbenches Verilator is included in oss-cad-suite 0.0.9 or later, but is not working properly. I have to solve some pendings bugs. First I will try to stabilize everything with oss-cad-suite 0.0.9 and once everything works ok, I will update to the latest 0.1.0