Apio verify/lint commands now process also all the testbench files.

[zapta]

Before this PR, apio verify and apio lint commands processed only the verilog module files (.v files which are not testbenches). This PR adds also all the testbench files. I believe that this is more useful and it was also the case before the adding support for multiple testbenches.

NOTE: for the link command, I don't have a verilator installed so tested until the point it invokes the verilator.

--> DEBUG!. Function process_arguments(). END
     Returns: 
      * ['fpga_arch=ice40', 'fpga_size=5k', 'fpga_type=up', 'fpga_pack=sg48', 'top_module=main']
      * upduino31
      * ice40

verilator --lint-only -Wno-TIMESCALEMOD deserializer.v main.v queue.v queue_pusher.v sensor_timing.v deserializer_tb.v queue_tb.v sensor_timing_tb.v
sh: verilator: command not found
scons: *** [hardware] Error 127

[Obijuan]

Verilator should be installed with the apio oss-cad-suite (0.0.9 or later). Currently is not working ok. I have to fix that Thanks for all your contribution. Are very very welcome! 😀️

[zapta]

Thank you!

I am new to FPGAs, waiting for my first board to arrive. I started a week or two ago with IceStudio and had a hard time. Then I found apio and it's so simple to install and easy to use. Exactly what I need.

On Wed, Feb 21, 2024 at 12:03 AM Juan Gonzalez-Gomez < @.***> wrote:

Verilator should be installed with the apio oss-cad-suite (0.0.9 or later). Currently is not working ok. I have to fix that Thanks for all your contribution. Are very very welcome! 😀️

— Reply to this email directly, view it on GitHub https://github.com/FPGAwars/apio/pull/344#issuecomment-1956087027, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAQVMQND7WUGHKWMEK3CWKDYUWS6VAVCNFSM6AAAAABDSN6Q26VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSNJWGA4DOMBSG4 . You are receiving this because you authored the thread.Message ID: @.***>