FPGAwars / apio

:seedling: Open source ecosystem for open FPGA boards
https://github.com/FPGAwars/apio/wiki
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[Proposal] Change Verible liner instead for Verilator. #358

Open zapta opened 4 months ago

zapta commented 4 months ago

This is a proposal for discussion.

The idea is to switch the linter from Verilator to Veriable.

https://github.com/chipsalliance/verible

Rationale In addition to a command line lint, Verible includes additional command line tools such as a verilog formatter or verilog aware diff, as well as a verilog language server that together with the the visual studio code verible plugin which provides verilog formatting and continuous linting while editing.

The actual code change to invoke verible instead of verilator is minimal. The main challange is to handle the automatic installation of the tools.

List of the Verible commands on my Mac OS:

verible-verilog-diff
verible-verilog-format
verible-verilog-kythe-extractor
verible-verilog-lint
verible-verilog-ls
verible-verilog-obfuscate
verible-verilog-preprocessor
verible-verilog-project
verible-verilog-syntax

@Obijuan , any thoughts?

Obijuan commented 3 months ago

I agree with this propolsal, although I have not used verible before I've checked the upstream oss-cad-suite package, but it does not include verible So my proposal is to include it directly in our oss-cad-suite apio package It may take some time to be included in apio

Any help with this task is very welcome