This is very useful software which I would like to use on another FPGA board via the exported verilog file. However, the port names in the verilog file are random and it is hard to follow which one is which. It would be good if the export routine would use assigned the port names in the graphical layout.
Jesus89
commented
6 years ago
This is very useful software which I would like to use on another FPGA board via the exported verilog file. However, the port names in the verilog file are random and it is hard to follow which one is which. It would be good if the export routine would use assigned the port names in the graphical layout.
Thank you very much!