I wish I could use an expressions with parameters when defining verilog block input/output ports size eg q[N-1:0] as long as particular parameter (N in our case) is listed in block parameters. Currently only numbers can be used.
Also currently user cannot create bus connection between ports of different sizes. If the size is changed and ports do not match, this connection is also deleted. This is not very convenient for using buses with parameters (with requirement of re-connection on every change) and this behavior could be changed: For instance one could always create the connection (even for mismatched ports), however if the width is evaluated to certain size (using parameter connected to a constant block or from default value) which differs to (evaluated) input port size, a small red cross close to unmatched input could indicate mismatch so that user can see that and change their constants (on either side) to fix it. Mismatched buses would be checked for as well as a first step on "verify" (build) prior additional verification to indicate possible mismatch error.
rokan51
commented
5 years ago
I wish I could use an expressions with parameters when defining verilog block input/output ports size eg q[N-1:0] as long as particular parameter (N in our case) is listed in block parameters. Currently only numbers can be used. Also currently user cannot create bus connection between ports of different sizes. If the size is changed and ports do not match, this connection is also deleted. This is not very convenient for using buses with parameters (with requirement of re-connection on every change) and this behavior could be changed: For instance one could always create the connection (even for mismatched ports), however if the width is evaluated to certain size (using parameter connected to a constant block or from default value) which differs to (evaluated) input port size, a small red cross close to unmatched input could indicate mismatch so that user can see that and change their constants (on either side) to fix it. Mismatched buses would be checked for as well as a first step on "verify" (build) prior additional verification to indicate possible mismatch error.