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FPGAwars / icestudio

:snowflake: Visual editor for open FPGA boards
https://icestudio.io
GNU General Public License v2.0
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Support for internal Oscillator as Clock (UPduino v1 & v2) #408

Open ertgtct opened 4 years ago

ertgtct commented 4 years ago

It would be great to be able to define one of the internal oscillators (the HF one in the best case) as input for the clock network. Then you dont have to route the clock discretely. An example can be found here: https://github.com/Idorobots/upduino-blinky/blob/master/blinky-extended/blinky.v (Credits go to Idorobots for the great example).

dabrams commented 4 years ago

I agree. The verilog code provided by lattice is

wire clk_48;
SB_HFOSC u_hfosc (
    .CLKHFPU(1'b1),
    .CLKHFEN(1'b1),
    .CLKHF(clk_48)
);

See https://github.com/FPGAwars/apio/issues/175

Laserlicht commented 4 years ago

I agree too.

A solution could be an "output-clk". Then you only have to use the code-block above once. It would be possible the prescale the 48Mhz to the usual 12Mhz before assigning for compatibility reasons.

jrwagz commented 1 year ago

I'll add my $0.02 here in saying this would be nice to have.

Idea: Is it possible to make your own custom block that you define the RTL for? In that case, it is just as simple as putting this RTL in that block?

   wire clk;
   SB_HFOSC inthosc(.CLKHFPU(1'b1), .CLKHFEN(1'b1), .CLKHF(clk));

Has anyone tried this already?

jrwagz commented 1 year ago

I just tested the above method, and it works.

image

Here is a link to the .ice file for this to use as a starter point:

https://gist.github.com/jrwagz/a2722055eea4211acd902e7548ee3905