Exporting Verilog code of subblock changes subblock

[BPJWES]

When exporting a subblock as verilog (requiring the user to be in the edit mode):

Icestudio changes the subblock ports to "FPGA ports" and converts the subblock to effectively a standalone block. This occurs when going from the edit mode ( the lock symbol is unlocked) to back to the read-only mode (the lock symbol should lock again).

The lock symbol disappears, and the program enters an unusable state as the original top level module disappears. This can possibly lead to a significant loss of work.

[cavearr]

Thanks for your feedback, i'm try to reproduce this bug and fix it thanks!

[cavearr]

Hi! please check if in the last WIP this is fixed!, i'm waiting for your news.

Thanks!

[BPJWES]

Platform: Windows 8.1 Version Icestudio: w202109060709

I can still reproduce the bug in the latest WIP

[TimRudy]

If this bug exists, it will be directed related to: https://github.com/FPGAwars/icestudio/issues/651, so I will find out during testing and will fix it

[cavearr]

Thanks Tim! i'm checking it , have you find a pattern to reproduce?

[TimRudy]

No I haven't looked at it. Just reviewing the Issues list :-)

On Thu, Apr 18, 2024 at 4:52 PM Carlos Venegas Arrabé < @.***> wrote:

Thanks Tim! i'm checking it , have you find a pattern to reproduce?

— Reply to this email directly, view it on GitHub https://github.com/FPGAwars/icestudio/issues/530#issuecomment-2065304236, or unsubscribe https://github.com/notifications/unsubscribe-auth/AA6CTIXC2OXZFRRU7IA2ATLY6AXBJAVCNFSM5CKBHOMKU5DIOJSWCZC7NNSXTN2JONZXKZKDN5WW2ZLOOQ5TEMBWGUZTANBSGM3A . You are receiving this because you commented.Message ID: @.***>

[cavearr]

Thanks Tim!