Physical dimensions of the Fader chip

[gwright83]

@bwrcbcr Is there a .spec file or other file giving the physical dimensions of the FADER IC? Perhaps there was one common to the CRAFT project chips?

[bwrcbcr]

Hi Greg,

We do not have a SPEC file; we tend to rely on the GDS as the golden information.

Thanks,

Brian

On Tue, May 26, 2020 at 9:57 AM Gregory Wright notifications@github.com wrote:

@bwrcbcr https://github.com/bwrcbcr Is there a .spec file or other file giving the physical dimensions of the FADER IC? Perhaps there was one common to the CRAFT project chips?

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-- Brian Richards Staff R&D Engineer Berkeley Wireless Research Center, U. C. Berkeley 2108 Allston Way Suite 200 Berkeley, CA 94704 O: (510) 710-1673 F: (510) 883-0270

[gwright83]

@caolen Do we still need a file giving the physical dimensions of the chip? If not, I will close this issue.

[caolen]

Greg, yes. I still need to get the actual step file for the chip. The extruded 3D body I placed as a model is just a placeholder. Thanks, Carl

From: Gregory Wright notifications@github.com Sent: Friday, June 5, 2020 6:10 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention mention@noreply.github.com Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

@caolenhttps://github.com/caolen Do we still need a file giving the physical dimensions of the chip? If not, I will close this issue.

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[gwright83]

@caolen Could we use a GDSII file of the top of the chip instead? The BWRC flow never generates a .STEP file.

[caolen]

Greg, I’m not familiar with the GDSII format. If someone knows how to convert that it to a *.STEP file that would work. Or, if someone has the shape, dimensions, and tolerances of the chip in a drawing, I can update the extruded 3D body for a more accurate model. Thanks, Carl

From: Gregory Wright notifications@github.com Sent: Monday, June 8, 2020 10:46 AM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention mention@noreply.github.com Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

@caolenhttps://github.com/caolen Could we use a GDSII file of the top of the chip instead? The BWRC flow never generates a .STEP file.

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[gwright83]

@caolen I will ask Brian Richards at the BRWC for the dimensions. I know that they were on one of the emails I reviewed with him when I was in Berkeley at the beginning of March.

[bwrcbcr]

All,

The only physical information that we have on the chip is GDS and submission spreadsheets; I am not familiar with other formats.

-Brian (From mobile)

On Jun 8, 2020, at 7:52 AM, Gregory Wright notifications@github.com wrote:

 @caolen I will ask Brian Richards at the BRWC for the dimensions. I know that they were on one of the emails I reviewed with him when I was in Berkeley at the beginning of March.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub, or unsubscribe.

[caolen]

Brian, so, if I can just get the numbers & units of width, length, height and dimensions of the chamfer at pin 1, I can work with these. Thanks, Carl

From: bwrcbcr notifications@github.com

Sent: Monday, June 8, 2020 12:31 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention mention@noreply.github.com Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

All,

The only physical information that we have on the chip is GDS and submission spreadsheets; I am not familiar with other formats.

-Brian (From mobile)

On Jun 8, 2020, at 7:52 AM, Gregory Wright notifications@github.com wrote:

 @caolen I will ask Brian Richards at the BRWC for the dimensions. I know that they were on one of the emails I reviewed with him when I was in Berkeley at the beginning of March.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub, or unsubscribe.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHubhttps://github.com/FaderOrg/Fader25_board/issues/18#issuecomment-640736663, or unsubscribehttps://github.com/notifications/unsubscribe-auth/APMOSPK5JHLU7KGGGXQIFALRVUG3JANCNFSM4NKVSHXA.

[bwrcbcr]

Hi Carl,

It appears that there is a misunderstanding about the FADER21 bare die; there is no package that would have a pin 1 marker or a chamfer; the orientation is solely identified by the asymmetric pattern of bumps on the die. Specialized equipment may be required for the flip-chip die attach.

Thanks,

Brian

On Mon, Jun 8, 2020 at 9:34 AM caolen notifications@github.com wrote:

Brian, so, if I can just get the numbers & units of width, length, height and dimensions of the chamfer at pin 1, I can work with these. Thanks, Carl

From: bwrcbcr notifications@github.com

Sent: Monday, June 8, 2020 12:31 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention < mention@noreply.github.com> Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

All,

The only physical information that we have on the chip is GDS and submission spreadsheets; I am not familiar with other formats.

-Brian (From mobile)

On Jun 8, 2020, at 7:52 AM, Gregory Wright notifications@github.com wrote:

 @caolen I will ask Brian Richards at the BRWC for the dimensions. I know that they were on one of the emails I reviewed with him when I was in Berkeley at the beginning of March.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub, or unsubscribe.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub< https://github.com/FaderOrg/Fader25_board/issues/18#issuecomment-640736663>, or unsubscribe< https://github.com/notifications/unsubscribe-auth/APMOSPK5JHLU7KGGGXQIFALRVUG3JANCNFSM4NKVSHXA>.

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-- Brian Richards Staff R&D Engineer Berkeley Wireless Research Center, U. C. Berkeley 2108 Allston Way Suite 200 Berkeley, CA 94704 O: (510) 710-1673 F: (510) 883-0270

[caolen]

Brian, my apologies for misunderstanding. The footprint for the chip includes a silkscreen overlay that suggests a “chamfer” at pin location “A1.”

Since there is no package that would have a pin 1 marker or a chamfer, I simply need the length, width and height of the chip package. Please provide these dimensions. Thanks, Carl

[A close up of a logo Description automatically generated]

From: bwrcbcr notifications@github.com Sent: Monday, June 8, 2020 1:26 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention mention@noreply.github.com Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

Hi Carl,

It appears that there is a misunderstanding about the FADER21 bare die; there is no package that would have a pin 1 marker or a chamfer; the orientation is solely identified by the asymmetric pattern of bumps on the die. Specialized equipment may be required for the flip-chip die attach.

Thanks,

Brian

On Mon, Jun 8, 2020 at 9:34 AM caolen notifications@github.com<mailto:notifications@github.com> wrote:

Brian, so, if I can just get the numbers & units of width, length, height and dimensions of the chamfer at pin 1, I can work with these. Thanks, Carl

From: bwrcbcr notifications@github.com<mailto:notifications@github.com>

Sent: Monday, June 8, 2020 12:31 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com<mailto:Fader25_board@noreply.github.com> Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com<mailto:carl.olen@nokia-bell-labs.com>; Mention < mention@noreply.github.commailto:mention@noreply.github.com> Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

All,

The only physical information that we have on the chip is GDS and submission spreadsheets; I am not familiar with other formats.

-Brian (From mobile)

On Jun 8, 2020, at 7:52 AM, Gregory Wright notifications@github.com<mailto:notifications@github.com> wrote:

 @caolen I will ask Brian Richards at the BRWC for the dimensions. I know that they were on one of the emails I reviewed with him when I was in Berkeley at the beginning of March.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub, or unsubscribe.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub< https://github.com/FaderOrg/Fader25_board/issues/18#issuecomment-640736663>, or unsubscribe< https://github.com/notifications/unsubscribe-auth/APMOSPK5JHLU7KGGGXQIFALRVUG3JANCNFSM4NKVSHXA>.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/FaderOrg/Fader25_board/issues/18#issuecomment-640738274, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAFMECE6LRCONZ4H4NERMWLRVUHHHANCNFSM4NKVSHXA .

-- Brian Richards Staff R&D Engineer Berkeley Wireless Research Center, U. C. Berkeley 2108 Allston Way Suite 200 Berkeley, CA 94704 O: (510) 710-1673 F: (510) 883-0270

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[gwright83]

@bwrcbcr Hi Brian, I think Carl just needs the bare die size for the physical model of the board (no "package").

[gwright83]

@bwrcbcr I think the thickness of the TSMC 16FFC die was 775 um. Is that true?

[gwright83]

@caolen I will measure the previous FADER IC die; the chip size is the same as the FADER 2.5 part. The thickness is 0.775 mm. I'll close this issue when I send you the dimensions.

[gwright83]

@caolen I measured the previous FADER2 die. It is 4.97 x 4.98 mm. Length and width tolerance is about +/- 0.01 mm (maximum). The variation in length and width is caused by the choice of dicing technique.

The die is thinner than the raw wafer. In the previous note, I said it was 0.775 mm. This in wrong --- the original wafer was that thickness, but the die has been thinned in a post-processing operation. The measured height from the back of the die to the top of the solder mask is 0.33 mm. For a typical solder mask thickness of 0.02 mm, this would give an overall die thickness (including bumps) of 0.35 mm.

[caolen]

Greg, thanks!

I will use this information to adjust the extruded 3D model for our U2 chip. You can now close this issue in the Git Hub.

Best regards, Carl carl.olen@nokia-bell-labs.commailto:carl.olen@nokia-bell-labs.com +1 908 516-0582 +1 614 406-5443 (mobile)

From: Gregory Wright notifications@github.com Sent: Wednesday, June 10, 2020 3:16 PM To: FaderOrg/Fader25_board Fader25_board@noreply.github.com Cc: Olen, Carl (Nokia - US) carl.olen@nokia-bell-labs.com; Mention mention@noreply.github.com Subject: Re: [FaderOrg/Fader25_board] Physical dimensions of the Fader chip (#18)

@caolenhttps://github.com/caolen I measured the previous FADER2 die. It is 4.97 x 4.98 mm. Length and width tolerance is about +/- 0.01 mm (maximum). The variation in length and width is caused by the choice of dicing technique.

The die is thinner than the raw wafer. In the previous note, I said it was 0.775 mm. This in wrong --- the original wafer was that thickness, but the die has been thinned in a post-processing operation. The measured height from the back of the die to the top of the solder mask is 0.33 mm. For a typical solder mask thickness of 0.02 mm, this would give an overall die thickness (including bumps) of 0.35 mm.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHubhttps://github.com/FaderOrg/Fader25_board/issues/18#issuecomment-642204811, or unsubscribehttps://github.com/notifications/unsubscribe-auth/APMOSPMHRPSLG7QOFFLBYILRV7LVVANCNFSM4NKVSHXA.