search

FaradayRF / FaradayRF-Hardware

Faraday hardware design files
https://www.faradayrf.com
Other
40 stars 7 forks source link

Update Hardware From Revision B Design/Testing #1

Closed kb1lqc closed 7 years ago

kb1lqc commented 7 years ago

Revision B hardware testing has identified several changes that would be ideal to incorporate with a board spin. Most of these are manufacturing related to help ensure a well designed PCB for production.

kb1lqc commented 7 years ago

Remove an RC filter from an ADC port to allow microphone use

I have decided to remove ADC5 RC filter to allow use with a microphone or other needs for unaltered ADC input. To do this, I've simply placed a 2 Ohm resistor at R25 and DNP'd C48. This allows eventual modification to a normal RC low-pass filter or just a capacitor in place of R25 to create a high-pass filter if speech recognition is benefited from that. Using 2 Ohms essentially gives me a zero Ohm resistor without adding a BOM line item.

Frc = 1/(2Pi(2 Ohms) * (25pF)) = 3.18 GHz

The resonant frequency of the 2 Ohm jumper with the CC430 ADC input capacitance of 25 pF creates a low-pass filter at 3.18 GHz which means the CC430 will be unaffected by this resistor.

image

It is important to note that this exposes the ADC input to ESD which could be an issue but typical MSP430 devices are rated for the Human Body Model

kb1lqc commented 7 years ago

Put Solder paste Layer on Q1 I actually cannot see why this came up as an issue. Looking at the actual OSHStencil Q1 clearly has holes for solderpaste. The KiCad PCBNew module editor also clearly shows Q1 having "Front Solder Paste" layers on each pad.

image

Looking at the image I took of a Faraday Rev B PCB just after solderpaste application clearly shows Q1 not covered in solder paste. I think the culprit is that either I didn't push down hard enough with the squeegee card when applying solderapaste or the holes are too small.

image

Marking this as complete. Production boards will be professionally pick and placed.

kb1lqc commented 7 years ago

Consider changing R17 to 360 Ohms for stronger filter I hooked up a Faraday Rev B to an old HP 6205C bench PSU and set the voltage to 1.395V. Faraday vin reads up to about 2.41V with it's internal Vref so this is roughly in the middle of the range. The HP power supply is also not the quietest supply, especially with almost no load.

Capturing roughly 30 minutes of telemetry I observed on average 2 bits of noise. The peak noise of the 1Hz telemetry appears to be about +-3 bits. Using an internal CC430 Vref and not using a super stable PSU or external reverence voltage to generate a test voltage I'm considering the CC430 ADC's to work well.

I doubt a 360 Ohm resistor (same as LEDs for BOM consolidation) will help much. Most noise I see on this quick check is < 1Hz. The screenshot below shows each datapoint equal to 1 second and the Y axis is showing each bit.

image

Update With 9V Battery on VCC

Looks good, only 3 bits of noise is readily apparent. I'm OK with this given the hardware design from the ADC perspective, it's not designed to be the most accurate ADC a CC430 could be :). This isn't a :rocket: ...

image

The spikes towards ground seem to be a firmware issue unrelated.

kb1lqc commented 7 years ago

Map GDO to a pin for eventual use off-board @kb1lqd What do you mean by bringing GDO off the board? Given the CC430 Family User's Guide the GDO pin might be able to be mapped to an external pin already.

Did you want Synchronous or Asynchronous support?

image

As it stands the GDO0 pin is on P1.0 which is currently used for GPS PPS signal.

Are you sure we can't simply use the port mapper internally to the CC430 to move GDO0 to a IO pin such as on P4.x?

kb1lqc commented 7 years ago

Make sure antenna is located such that it doesn't hit DOUT headers

img_0886

img_0888

Marking this as solved and doing nothing. Stack any extra boards on the bottom or if they are stacked on the top then design in a cutout for the antenna. Moving the antenna is too big of a problem give 4 layers and the amount of IO routing in that area of the board.

kb1lqc commented 7 years ago

Validate USB Multiplexing & Negotiation Circuitry

To check this circuit out I need to perform the following hardware changes

image

Then I will need to configure the FTDI FT PROG to configure CBUS3 of U6 to be Power Enable. This will auto-configure into high power mode before turning on Faraday when plugged into a USB port. It's advantageous since this is USB compliant and overall causes less inrush.

kb1lqc commented 7 years ago

Per my testing on #5 I've decided to use the FTDI USB negotiation and soft-start circuit. This ensures we are conservative with USB power on and minimize inrush events that could damage Faraday or damage a USB port powering Faraday.

I've removed R7 and populated C15 and U11 to perform the inversion necessary to have the FT230X control the MIC94072YC6.

image

kb1lqc commented 7 years ago

Move Via near CC430 exposed pad which causes copper to be pulled back Offending via shown below from Rev B build images image

This is the GPS standby control signal. So low speed on/off and therefore can be routed however I need. image

Fixed

image

As shown above I routed the standby signal as well as two adjacent signals (HRST, P3_6) to move STDBY up to 15 mils from the CC430 center exposed pad. This should fix any issue of the copper being pulled back for the via.

kb1lqc commented 7 years ago

Check NUF2101MT1G footprint carefully

Looking at it I can't see what I thought was wrong? Looks fine... U10: image

Comparing to the datasheet suggested land pattern: image

Pad Size

image

This is likely due to me basing my footprint on one particular suggested footprint which differs from another vendor. This in general shouldn't be an issue for standard footprints such as this TSOP-6.

Checking pad spacing the Y spacing between pads it looks fine at 0.95mm. The X spacing is a little wide at 2.62mm but that's well within reason for having slightly longer pads to make up for that. This part will fit squarely on these pads.

kb1lqc commented 7 years ago

Check MIC94072YC6 (U12) footprint as it looks very close to solder bridge prone

U12 looks like it's a bit close to shorting between pins. There's almost no soldermask between pins! Maybe this is OK but whew...

image

Footprint

This footprint is based on the Linear Technology footprint for a SC70-6.

image

image

Pad Y: 1.00mm Pad X: 0.47mm

This is exactly what the footprint wants. So looking at spacing now:

Pad Y Spacing: 1.8mm Pad X Spacing: 0.65mm

This is also exactly what the LTC footprint asks for, copper looks good.

Soldermask

It looks like OSHPark, who made the Rev B boards, has a minimum of 2.5 mil soldermask sliver for their prototype 4 layer boards. See their specs. I'm going to assume OSHPark doesn't use a fancy process to make their boards (safe assumption) which means 2.5mils is 0.0635mm.

I measured 0.178mm between pads on my footprint model. image

When looking at the PCB prior to populating it, the pads of U12 seem fine, there's a decent amount of soldermask there. I may see better results when the proper amount of solderpaste is applied, I likely used too much.

image

kb1lqc commented 7 years ago

Double-check orientation of X2 versus datasheet and footprint/pinout

The 26 MHz crystal, X2, on Faraday was originally placed backwards. This crystal is the ABM8G-10572. Here's the position on the board design: image

and here is my initial placement which was 90 degrees off: image

The top view looking down through the package as if the ceramic wasn't present we should expect this pinout: image

Conclusion

It's obvious that my footprint agrees with the top view as it should, my orientation on the board is 180 degrees different but rotating the suggested footprint would result in the exact same, and correct, placement as I realized after populating the board.

Now why did I think I was right when populating at 90 degrees off? It appears that the chamfer can switch between pin 1 and pin 4, if the chamfer was on pin 4 instead of pin one then I would absolutely have placed the crystal the way I did. image

Solution

So this then comes down to not judging orientation by the chamfer. Instead if I simply ensure that my library footprint is compliant with IPC-7351 Level A then there is no need to look for the chamfer, image

Keeping this orientation standard and using a pick and place machine results in either pin 1 being placed on pad 1 or with 180 degrees rotation in the tape and reel pin 3 would be placed on pad 1. This however is completely fine as pin 1 would connect to pad 3 and that still connects the crystal correctly.

Looking at my library I have pin 1 in the upper left quadrant 1 of the IPC spec. The datasheet shows the tape and reel orientation with long edges vertical when holding tape horizontal. According to the Mentor Graphics blog post oscillators (multi-pin) are in tape and reel packages with pin 1 in the lower left quadrant.

It seems like this is purely up to me telling the manufacturer that I follow IPC-7351 Level A with my footprints and that they should observe good judgment on tape an reel orientations. Worst-case the first batch of boards needs to be reworked and this is a pretty easy part to rework with a heat gun.

kb1lqc commented 7 years ago

Map GD0 to a pin for eventual use off-board

Looking into this from @kb1lqd comments on #6, I will be using that Issue Ticket to track changes to the PCB. This is looking like it will absolutely be the biggest change to the entire board between Rev B and Rev C...

As noted in #6, I swapped some P3 and P4 channels which turned out to be relatively simple since the signal traces routed to the same general area of the board. I haven't extensively checked this change but first indications show it to be straightforward and complete.

kb1lqc commented 7 years ago

Confirming successful changes to Revision C hardware

Inductor moved over to L0603 footprint image image

Part looks fine on board image

Checked out fine in previous comment about this footprint

Looks good to me, my moved pulled it away from the pad even with further work in the area image

Q1 is correctly solderpasted

Orientation is fine per pin 1 having the chamfer. Professional pick and place should remove human eye coordination error.

Keeping 2 Ohm resistor with standard 0.1uF decoupling capacitor. No need to change.

ADC5 replaced series resistance with 2 Ohm resistor while parallel capacitor DNP'd

image

image

image

Antenna nor does RF SMA cable become obstructed by IO headers when installed.

@kb1lqd brought up the flash and was able to fix a few initial errors in his firmware to get it shaken out.

Complete image

Complete image

kb1lqc commented 7 years ago

Checked all updates. Appear OK. Closing.

kb1lqc commented 7 years ago

Documenting that running a Freedfm.com test caught a soldermask pullback error! The 0603 L10 component I placed in the CC1190 section is apparently missing a soldermask relief on the soldermask gerbers:

image

Yup, clearly visible. Will update! image

kb1lqc commented 7 years ago

Reopened to document several recent updates.

X2 footprint updated to let Pin 1 silkscreen indicator print on PCB Was previously under pin 1 on C9 so it would never print image

U4 CC1190 Keepout Area Copper Pour Removed L10 moving to 0603 let copper pour under the keepout area. While this is fine, I want to not let this change happen from Rev B to Rev C.

image

Copper Ground near C28 and L9 Pulled Back As shown in the image above of U4, you can see that the copper ground pour on the top layer no longer tries to fill in between the pads. I decided to keep the path of RF clear of any encroachments.