Test LFXTAL1 With Internal Capacitors

[kb1lqd]

Test the CC430's ability to operate with these capacitors DNP'd.

[kb1lqd]

Faraday Unit Setup

SN: 3

I removed C7 and C8 capacitors from REV B1 that capacitively load the low frequency crystal X1. These are 18pF capacitors that should be able to be supplied by internal capacitors from the CC430.

Initial Boot with XCAP_0 Internal capacitor

Looks like it's booting and giving UART data! The frequency is likely offset a bit. Even 18pF was a conservative estimate. XCAP_0 is 2pF of internal load capacitance + parasitic trace capacitance.

Do note that it looks like a long time ago I skipped this XTAL1 and set it to the internal VLFO that is less accurate (especially over temperature) due to XTAL1 booting issues. Looks like I may not actually be using it yet.

CC430 Users Guide - LFXTAL1 Internal Capacitance

Internal capacitors are provided by the CC430 ranging from 2pF to 12pF.

Testing

I suscessfully testing updated boot initialization code that ensured all clocks properly booted and that ACLK utilized the LFXTAL1 with an internal capacitance of 12pF (XCAP_3).

I checked the crystal datasheet and a nominal load capacitance is 12.5pF, I seem to recall the CC430 datasheet rule of thumb the stray parasitic capacitance around 2pF for the traces to the crystal. I'm implemented 12pF+parasitic since we know 18pF worked and any tolarance or temperature will likely vary near nominal. We can try lowering to 9pF later...

NOTE: All works fine right now but we might be able to fine tune the UART timing for baudrate given a slightly better accuracy for frequency reference. Not a huge deal right now.

void init_UCS(void){
    //Set Vcore for intended operating range | VCORE = 2 needed for RF module boot
    SetVCoreUp(2);

    // Initialize LFXT1
    P5SEL |= 0x03;                            // Select XT1
    UCSCTL6 |= XCAP_3;                        // Internal load cap

    __bis_SR_register(SCG0);            // Disable the FLL control loop
    UCSCTL0 = 0x0000;                   // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_7;                // Select DCO range 16MHz operation
    UCSCTL2 = FLLD_1 + 487;             // Set DCO Multiplier for 16MHz
                                        // (N + 1) * FLLRef = Fdco
                                        // (487 + 1) * 32768 = 16MHz (REFOCLK = internal 32768Hz)
                                        // Set FLL Div = fDCOCLK/2
    UCSCTL3 |= SELREF_2 + FLLREFDIV_0;  // Set DCO FLL reference = REF0CLK/1

    __bic_SR_register(SCG0);                  // Enable the FLL control loop

    /*
     * Allow DCO taps and FLL to settle after initialization.
     * Worst-case MCLK cycles = FLLDIV x 32 x 32 x FLLREFCLK
     *
     * Cycles = 1 x 32 x 32 x 32768 = 33554432 cycles
     */
    __delay_cycles(33554432);

    /*
     * Set clock sources
     * ACLK = XT1CLK (32768 Hz)
     * SMCLK = DCOCLKDIV (8MHz FLL controlled)
     * MCLK = DCOCLK (16MHz)
    */
    UCSCTL4 |= SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLK; // ACLK = LFXTAL1, SMCLK = DCOCLKDIV, MCLK = DCOCLK

  // Loop until XT1,XT2 & DCO stabilizes
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  __no_operation();

}

The code booted OK and I was able to get UART data from the device OK.

[kb1lqd]

I updated the firmware master in commit (13833d0b36bc32281c88fcfc904557dc15d56363) that includes the updated internal capacitance 12pF crystal load. Make sure to remove the capacitors from the other boards we currently have!

Also, I committed to master. SORRY!