Rev D1 Gerber Review

[kb1lqc]

Simply Looking at the board to see if everything makes sense. Very 10k foot view stuff.

[kb1lqc]

Top Layer With Soldermask & Solder Paste

• Overall looks good nothing seems extremely off or erroneous
• It's obvious that the 4 mil soldermask clearance causes may of the SOT, QFN, and USB type parts to simply not put soldermask in a big block around the pins as they are so close.

The CC1190 RGV Footprint Working with PCB:NG it became apparent that the soldermask slivers needed to be dealt with. The problem was that the corners of the corner pads were < 4 mils from each other. This prompted me to place four rectangles 4milx10mil of soldermask only at 45 degree angles between these pads to force the slivers to be removed. Below this soldermask layer is green.

CC430 RGC Footprint Similar to the CC1190, the 4 mil clearance of soldermask caused the pins to largely be blocked out. Naturally the corners formed areas where the soldermask areas were flowing into each other.

Power Supply Net Tie

• The net-tie doesn't have solderpaste but does have soldermask pullback as shown with a lack of blue solderpaste layer.
• This prevents DFM checks from marking an error for soldermask over pad.
• [ ] I should consider removing this and just dealing with the DFM error... Thoughts @kb1lqd ?

[kb1lqc]

Top Layer Vs Inner A Layer

• Inner A layer provides ground plane for the entire board and it appears to be almost everywhere sans vias on a different net and the outer CGND route.
  • Copper looks pulled back where GPS antenna is

[kb1lqc]

Inner A and Inner B Layers

• Inner A provides groundplane while Inner B provides power and RF routing, however Inner B is closer to the bottom (13 mil) than Inner A (28 mil) so it's a weaker reference.
• The RF route on Inner B appears to be completely covered with a ground plane on Inner A except where via clearance is necessary and that's expected.
• ⚠️ 3.3V routing on Inner B seems a bit constrained but as shown with green markings below there appears to be a decent amount of copper passing through, certainly a lot for ~700mA.

[kb1lqc]

Inner B to Bottom Layer

• Inner B largely routes power around the PCB but also RF.
• Lines running on bottom layer don't need ground on Inner B since Inner A provides the ground reference. However this is not the case for impedance sensitive RF lines!
• All bottom layer traces running over 3.3V pour are low speed, not too worried. Fastest might be PPS signal from GPS and even that we're not expecting super high speed edges for functionality. Pretty sure we can deal with a few ns.
• RF traces on Inner B only 13 mils away from bottom layer so tightly coupled and must be ground!

RF traces look good.

[kb1lqc]

Bottom Layer with Soldermask and Solderpaste

• Looks good!
• Test points appear to be free of soldermask
• JTAG connector looks good
• Mounting and through hole connectors look good too

[kb1lqc]

Component Courtyards and Front Silkscreen

• OSHW logo could move a little to the right ❔
• Otherwise looks great, no overlapping component courtyards or reference designators

[kb1lqc]

Component Courtyards and Bottom Silkscreen

• I forgot to mention the ECO1 layer which has courtyards on it has both top and bottom courtyards so one must mentally distinguish from components on the top and bottom.
• [x] 3.3V test point text is far away from test point ⚠️
• [x] JTAG pad text is not lined up well ⚠️
• [x] Add a note about voltages > 3.3V on ext mic/ref pin can damage Faraday! ⚠️

[kb1lqc]

Sat down with @kb1lqd and reviewed Gerbers with him. We found a few items that I changed which were non-critical but worth changing now:

• [x] GPS Antenna Silkscreen on top/bottom updating
• [x] VCC and GND Silkscreen on top for power header row marking better
• [x] CC1190 pin 1 and 16 still had manual soldermask pullback settings

Fixed in the latest commit with new gerbers and and updated pick and place files with the BOM: https://github.com/FaradayRF/FaradayRF-Hardware/pull/41/commits/f2f15c6f3cfcc669f786e9bba21574d92cefe05a