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Fazail333 / Vector-Co-processor

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Vector Load Store unit #14

Open Zawaher-Bin-Asim opened 3 weeks ago

Zawaher-Bin-Asim commented 3 weeks ago

Make the load store unit for the vector processor keeping in view the effects of the variable inputs like LMUL ,SEW , VLMAX . Provide the rtl code with the randomized testing . Also , provide the proper documentation including the datapath and block digram .

Zawaher-Bin-Asim commented 3 weeks ago

@Fazail333 you should output a load_req and store_req signal to the memory in order to load and store in the memory

Zawaher-Bin-Asim commented 3 weeks ago

i have added ld_req and st_req signals to vlsu so kindly rebase your branch and implement the logic of the ld_req and st_req in the vlsu