Question about U3 - LM3480

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Hi David, At K-2 to K-3 of your receiver schematic.pdf can I delete the u3, c25 
and connect 3V3FX2 to c29 as power supply? Thanks! 

Original issue reported on code.google.com by extrava...@gmail.com on 9 Jul 2014 at 2:06

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This is the only project I've found so far for building a 978MHz UAT receiver 
but there don't seem to be any recent posts, so I'm posting here in case anyone 
can point me to something active. I'd like to find out how much it would be to 
scratch-build this device, and whether there would be interest in forming a 
group to purchase bulk components and investigate other ways of making it 
easier and cheaper.

I have been a volunteer on the free open-source Avare aviation app 
(https://play.google.com/store/apps/details?id=com.ds.avare) and am interested 
in coming up with an affordable UAT receiver option. Avare already works great 
with commercial products like the Dual and others, and there's a new open 
source RTL-SDR app for 1090 TIS-B on Avare. But apparently UAT on RTL-SDR is a 
problem due to the data rate. I'll watch this page for a day or two, but it 
would be much easier to connect via the Avare forum for followup: 
https://groups.google.com/forum/#!forum/apps4av-forum

Original comment by John...@gmail.com on 14 Aug 2014 at 11:50

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Hi David & John. I made a pcb, gathered the components, solder them together so 
far as the attachment picture shows. But there is at least 2 question I think: 
    1) Must the 12.288Mhx xrystal be a sine wave xrystal? I only find a square wave 12.288Mhz one.
    2) At the fx2lp side, I am still working on the firmware to drive ML2722 to work in test mode. The TD_Init function is shown as below, But it seems can not init correctly, the fx2lp hangs when plugged in. And still have no idea how to set the ml2722 registers through the '3 wire' bus of ml2722 from fx2lp. Could there be some hint from David? Thanks!

//--------------------------start---------------------------
void TD_Init(void)             // Called once at startup
{
   // set the CPU clock to 48MHz
   CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   // set the slave FIFO interface to 48MHz
   IFCONFIG |= 0x43;

  // Registers which require a synchronization delay, see section 15.14
  // FIFORESET        FIFOPINPOLAR
  // INPKTEND         OUTPKTEND
  // EPxBCH:L         REVCTL
  // GPIFTCB3         GPIFTCB2
  // GPIFTCB1         GPIFTCB0
  // EPxFIFOPFH:L     EPxAUTOINLENH:L
  // EPxFIFOCFG       EPxGPIFFLGSEL
  // PINFLAGSxx       EPxFIFOIRQ
  // EPxFIFOIE        GPIFIRQ
  // GPIFIE           GPIFADRH:L
  // UDMACRCH:L       EPxGPIFTRIG
  // GPIFTRIG

  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
  //      ...these have been replaced by GPIFTC[B3:B0] registers

  // default: all endpoints have their VALID bit set
  // default: TYPE1 = 1 and TYPE0 = 0 --> BULK  
  // default: EP2 and EP4 DIR bits are 0 (OUT direction)
  // default: EP6 and EP8 DIR bits are 1 (IN direction)
  // default: EP2, EP4, EP6, and EP8 are double buffered

  // we are just using the default values, yes this is not necessary...
  // EP1OUTCFG = 0xA0;
  // EP1INCFG = 0xA0;
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA0;
  SYNCDELAY;                    
  EP4CFG = 0x00;
  SYNCDELAY;                    
  EP6CFG = 0xE0;
  SYNCDELAY;                    
  EP8CFG = 0x00;

  // out endpoints do not come up armed

  // since the defaults are double buffered we must write dummy byte counts twice
  SYNCDELAY;                    
  FIFORESET = 0x80;                // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;                    
  FIFORESET = 0x02;
  SYNCDELAY;                    
  FIFORESET = 0x06;                // arm EP4OUT by writing byte count w/skip.
  SYNCDELAY;                    
  FIFORESET = 0x00;    

  SYNCDELAY;                    
  PINFLAGSAB = 0xE6;                // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;                    
  PINFLAGSCD = 0xF8;
  SYNCDELAY;                    
  PORTACFG |= 0x00;                // arm EP4OUT by writing byte count w/skip.
  SYNCDELAY;                    
  FIFOPINPOLAR = 0x00;    
  SYNCDELAY;                    
  OEA |= 0x0F;

  EP2FIFOCFG = 0x01;
  SYNCDELAY;

  EP6FIFOCFG = 0x09;
  SYNCDELAY;                    

  PORTCCFG = 0x00;            
  PORTECFG = 0x00;
  OEC = 0x00;
  OEE = 0xFF;

  PA0 = 1;

  // BOOL enum_high_speed = FALSE;
  // enable dual autopointer feature
  //AUTOPTRSETUP |= 0x01;

}
//---------------------------end-------------------------- 

Original comment by extrava...@gmail.com on 31 Aug 2014 at 3:32

Attachments:

• IMG_20140824_113058_s.jpg

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another pic

Original comment by extrava...@gmail.com on 31 Aug 2014 at 12:01

Attachments:

• IMG_20140824_113058_ss.jpg