Closed gschadow closed 1 year ago
Thank you for drawing my attention to MRISC32.
The ForwardCom instruction set has many features that makes it more efficient than other instruction sets. See https://forwardcom.info/ for the details.
The next step will be an FPGA implementation. I don't have the time for this right now because I am busy with other projects. Maybe I can find some students who will make this as a project.
Next, people might start to use ForwardCom for university projects and build a community around it, in the same way as they are doing with https://riscv.org/. RISCV is for small low-end projects, ForwardCom is for larger scalable projects and vector processor projects.
The intuitive high-level assembly language will make projects easier. Next, we need to make a Clang compiler back end.
I imagine that the first applications for ForwardCom will be in FPGA soft cores. It is quite expensive to develop an ASIC chip.
You are asking how ForwardCom might revolutionize the world? Well, if for some reason x86 is collapsing under its own weight, if people need a non-proprietary instruction set for legal reasons, if people need an efficient scalable instruction set for large vector processors, or if people need a new instruction set for any other reason, ForwardCom is ready to be applied.
If people need a non-proprietary instruction set, they probably also need an non-proprietary operating system, for example Linux. The OS may need modifications if you want to take advantage of the new efficient memory management system.
The ForwardCom project doesn't need money in the current situation, it needs people!
I had also come across your ISA a while back when researching ISA design. Your project has helped me learn so much already. Currently I am studying for a degree in computer science and will be starting my focus courses soon and I would love to create a working version of your ISA on my FPGA. Are you ok if I try and take on creating a working version of your ISA? It would be great if I could contribute and help further the development of your ISA. Maybe even one day seeing this as a common option amongst other processors and their ISAs.
Yes, you are very welcome to make an FPGA softcore. You may look at my emulator to get inspiration on how to decode the instructions. You may split the execution unit into lanes of 64 or 128 bits each so that you can expand it just by adding more identical lanes.
https://opencores.org/ is a good place to look for resources and help
I am starting to make a softcore now. Any help will be appreciated.
Hi, first, I feel compelled to congratulate you about the breath and depth of your prolific work of which I came to see a glimpse today. People who publish in anthropology, evolutionary biology, software and hardware are rare in this world. I am amazed.
Secondly I am looking at your ForwardCom project and this idea of designing a new CPU from scratch, one that combines the best we know today and cuts the baggage of 50 years of history.
I found you via a different, similar project, called MRISC32 by a certain Marcus Geelnard. Here is a link: MRISC32 A Vector-First CPU Design, a Homepage and a GitHub project.
I would like to know how you see your work compare with this. And now I am going to ask you the same list of questions that I asked Marcus Geelnard: