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Fraunhofer-IMS / airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
https://www.airisc.de
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[.github] add SW build workflow #14

Closed stnolting closed 1 year ago

stnolting commented 1 year ago

This PR add another GitHub workflow to compile the default demo application in bsp/example for providing up-to-date executables. The *.elf and *.asm artifacts are available as GitHub workflow assets.