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Fraunhofer-IMS / airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
https://www.airisc.de
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BlockRAM configuration issue #16

Open domenico-rgs opened 1 year ago

domenico-rgs commented 1 year ago

I'm trying to synthetize, implement and generate the bitstream for the NexysVideo board.

Firstly, I tried to do it manually following the instructions on the user guide . It worked but if I try to simulate the top level design with the test bench all the tests fail.

Then I did the same using the tcl script and the Makefile, everything worked fine and all the tests have passed. I found out that the only differences betweeen the two project created are the options in the BlockRAM that the user guide says to set as:

Generate address interface with 32 bits : yes
Common Clock                            : no

while the xcix file contains them set as:

Generate address interface with 32 bits : no
Common Clock                            : yes

In deed if I change the options as the latter the TB passes. Is there a problem with the TB or the configuration specified in the user guide is wrong ?

The image below shows the errors I obtain when executing the TB using 32 bit address interface and no common clock. vivado-error

stnolting-ims commented 1 year ago

Hey there!

Sorry for the late reply. I think this is just a misunderstanding in the user guide and we will check that. However, your setup is working now as expected, right?

domenico-rgs commented 1 year ago

Hey there!

Sorry for the late reply. I think this is just a misunderstanding in the user guide and we will check that. However, your setup is working now as expected, right?

Hello, thanks for you reply! Currently I cannot answer you because since I am trying to replicate the setup on a Nexys4 DDR board (that does not have an integrated JTAG interface, as the Arty-A7) I am waiting to have a JTAG dongle to check. Anyway I will let you know. In the meanwhile, I can say that with the common clock enabled and no 32-bit interface the test bench passes all the tests and the board programming goes well.