search

Fraunhofer-IMS / airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
https://www.airisc.de
Other
82 stars 18 forks source link

Add CI - Simulation #5

Closed stnolting closed 2 years ago

stnolting commented 2 years ago

This is a very first version of a CI workflow that runs a simulation of the default processor testbench. The final simulation log is checked for a key word to validate the simulation was successful (this can also be used to set a badge status in the front-side README).

This first setup uses Icarus Verilog, but might be replaced by Verilator as Icarus Verilog is not intended for larger designs (the elaboration step takes quite long).

stnolting-ims commented 2 years ago

Working! :+1:

Ready to be merged.